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hd66770 rev.1.1 / april 2002 1 hd6677 0 396-channel source driver with internal ram for tft 65536-color displays rev. 1 . 1 april 2002 description the hd66770, 396-channel source driver lsi, displays 132rgb-by-176 dot graphics on tft displays in 65,536 colors. it is for driving tft color lcd displays to a maximum of 132rgb by 176 dots, in combination with the gate driver, hd66771 and power supply ic, hd667p00. the hd66770 ? s bit- operation functions, 16-bit high-speed bus interface, and high-speed ram-write functions enable efficient data transfer and high-speed rewriting of data to the graphics ram. the hd66770, hd66771 and hd667p00 have various functions for reducing the power consumption of a lcd system. hd66770 has a low-voltage operation (1.8 v min.) and an internal ram to display a maximum of 132rgb-by-176 dot color, and the hd66771 has 288 pins of tft gate wiring driver circuit. also, hd667p00 has the internal booster that generates the liquid crystal voltage, breeder resistance and the voltage follower circuit for liquid crystal driver. hd66770 incorporates a circuit that interfaces with the hd66771/hd667p00, it can set instructions for hd66771/hd667p00. in addition, precise power control can be achieved by combining these hardware functions with software functions, such as an 8-color display and standby and sleep mode . this lsi is suitable for any medium-sized or small portable battery-driven product requiring long-term driving capabilities, such as digital cellular phones supporting a www browser, bi-directional pagers, and small pdas. features 132rgb x 176-dot graphics display lcd controller/driver for 65, 536 tft colors (when hd66771/hd667p00 are used) 16-/8-bit high-speed bus interface and serial peripheral interface (spi) high-speed burst-ram write function writing to a window-ram address area by using a window-address function bit-operation functions for graphics processing: write-data mask function in bit units logical operation in pixel unit and conditional write function various color-display control functions: 65,536 colors can be displayed at the same time ( gamma adjust included ) vertical scroll display function in raster-row units
hd66770 rev.1.1 / april 2002 2 low-power operation supports: ? vcc = 1.8 to 3.3 v (low-voltage range) ? ddvdh = 4. 5 to 5. 5 v (liquid crystal drive voltage) ? power-save functions such as the standby mode and sleep mode ? partial lcd drive of two screens in any position ? maximum 12-times step-up circuit for liquid crystal drive voltage (hd667p00) ? voltage followers to decrease direct current flow in the lcd drive bleeder-resistors (hd66770) built-in circuit for interfacing with the gate driver, hd667 71 and power supply ic, (hd667p00) maximum 132rgb-by-176-dot display in combination with the hd66771 and hd667p00 internal ram capacity: 46, 464 bytes 396 -source liquid crystal display driver n-raster-row inversion drive ( it is possible to lcd driving voltage inversion reverse the polarity in every selected raster-row.) internal oscillation and hardware reset shift change of source drive r type numbers type number external appearance hcd667a70bp die with gold bump (straight output arrangement) hcd667b70bp die with gold bump (laced output arrangement)
hd66770 rev.1.1 / april 2002 3 h d667 70 block diagram description v60n,v62p,v62n,v63p,v63n control register (cr) address counter (ac) source driver cpg rs rw/rd* e/wr*/scl vcc osc1 osc2 7 16 16 im2-1, im0/id reset * db0/sdi, db1/sdo, to db15 cs* 16 bit operation 16 m a/c circuit read data latch 16 16 16 test grayscale voltage generator index register (ir) 16 cl1 flm m vdh vcom gcl gda gcs* 16 eq latch circuit latch circuit write data latch 64 gamma adjusting circuit dcclk system interface ?e 16 bit ?e 8bit ?e serial peripheral (spi) common driver interface (serial) graphic ram (gram) 46,464 bytes s1 to s396 v0-63 gnd timing generator disptmg latch circuit ddvdh v8,v20,v43,v55 vgs test1 ts7-0 vtest v0,v1p,v1n,v3p,v3n,v60p, figure 1: hd66770 block diagram description
hd66770 rev.1.1 / april 2002 4 pin functions table 1 pin functional description signals number of pins i/o connected to functions im2-1, im0/id 3 i gnd or v cc selects the mpu interface mode: when a serial interface is selected, the im0 pin is used as the id setting for a device code. cs* 1 i mpu selects the hd66770: low: hd66770 is selected and can be accessed high: hd66770 is not selected and cannot be accessed must be fixed at gnd level when not in use. rs 1 i mpu selects the register. low: index/status high: control e/wr*/scl 1 i mpu for a 68-system bus interface, serves as an enable signal to activate data read/write operation. for an 80-system bus interface, serves as a write strobe signal and writes data at the low level. for a synchronous clock interface , serves as the synchronous clock signal. rw/rd* 1 i mpu for a 68-system bus interface, serves as a signal to select data read/write operation. low: write high: read for an 80-system bus interface, serves as a read strobe signal and reads data at the low level. db0/sdi 1 i/o mpu serves as a 16-bit bi-directional data bus. for an 8-bit bus interface, data transfer uses db15-db8; fix unused db7-db0 to the vcc or gnd level. for a clock-synchronous serial interface, serves as the serial data input pin (sdi). the input level is read on the rising edge of the scl signal. db1/sdo 1 i/o mcu serves as a 16-bit bi-directional data bus. for an 8-bit bus interface, data transfer uses db15-db8; fix unused db7-db0 to the vcc or gnd level. for a clock-synchronous serial interface, serves as a serial data output pin (sdo). successive bit values are output on the falling edge of the scl signal. db2-db15 14 i/o mpu serves as a 16-bit bi-directional data bus. for an 8-bit bus interface, data transfer uses db15-db8; fix unused db7-db0 to the vcc or gnd level. (continue to the next page ) mpu interface mode im2 im1 im0/i 68-system 16-bits bus interface "gnd" "gnd" "gnd" 68-system 8-bit bus interface "gnd" "gnd" "vcc" "gnd" "gnd" 80-system 16-bit bus interface "vcc" 80-system 8-bit bus interface "vcc" "gnd" "vcc" serial peripheral interface (spi) "vcc "gnd" id
hd66770 rev.1.1 / april 2002 5 signals number of pins i/o connected to functions s1 ? s 396 396 o lcd output signals are for liquid crystal voltage. the ss bit can change the shift direction of the source signal. for example, if ss = 0, ram address 0000 is output from s1. if ss = 1, it is output from s 396 . s1, s4, s7, ... display red (r), s2, s5, s8, ... display green (g), and s3, s6, s9, ... display blue (b) (ss = 0). cl1 1 o hd66771 the one-raster-row-cycle pulse is output. m 1 o hd667p00 the ac-cycle signal is output. flm 1 o hd66771 the frame-start pulse is output. eq 1 o hd667p00 indicate setting of the vcom output to its high-impedance state during transitions of vcom when vcom is being ac- cycled. low: vcomh or vcoml is being output on the vcom pin. high: vcom pin is in high-impedance state disptmg 1 o hd66 771 gate off signal in the partial display ? low ? : output voff signal ? high ? : output normal signal dcclk 1 o hd667p00 outputs clock for the step-up circuit of hd667p00 . gcl 1 o hd66771 hd667p00 clock signal for a serial transfer of register setting value s to the gate driver and the power supply ic . data is output on the falling edge of this clock. gda 1 o hd66771 hd667p00 data signal for serial transfer as register setting value s to the gate driver and the power supply ic . gcs* 1 o hd66771 hd667p00 chip-select for the hd66771 and hd667p00. low: the hd66771/hd667p00 are selected and can receive a serial transfer data . high: the hd66771/hd 667p00 are not selected and cannot receive a serial transfer data . ddvdh 1 i hd667p00 input power supply for lcd drive circuit, which can be provided by hd667p00. ddvdh : +4.5 to +5.5 v vdh 1 i hd667p00 this is the standard level of grayscale voltage generator, which can be provided by hd667p00. vdh (max.) : ddvdh ? 0.5 v vcom 1 i hd667p00 it is a signal for equalizing function. all lcd driver ? s outputs (s1 to s396) are short to vcom level (hi-z) in eq = ? high ? period. must be left disconnected when vcoml < 0 v. v cc , gnd 2 ? power supply v cc : + 1.8 v to + 3.6 v; gnd (logic): 0 v osc1, osc2 2 i or o oscillation- resistor connect an external resistor for r-c oscillation. when input the clock from outside , input to osc1, and open osc2. reset 1 * reset2* 2 i mpu or external r-c circuit reset pin. initializes the lsi when low. must be reset after power-on. (continue to the next page )
hd66770 rev.1.1 / april 2002 6 signals number of pins i/o connected to functions vccdum o input pins outputs the internal v cc level; shorting this pin sets the adjacent input pin to the v cc level. gnddum o input pins outputs the internal gnd level; shorting this pin sets the adjacent input pin to the gnd level. dummy ? ? dummy pad. must be left disconnected. test 1 i gnd test pin. must be fixed at gnd level. v0, v1p, v3p, v60p, v62p, v63p 6 i/o stabilized capacitor when built-in op-amp is on (sap2-0= ? 001 ? , ? 010 ? , ? 011 ? , ? 100 ? , ? 101 ? ), it is for outputs of positive polar (v0 is for positive/negative polar) built-in op-amp. connect condenser and stabilize the condition. v1n, v3n, v60n, v62n, v63n 5 i/o stabilized capacitor when built-in op-amp is on (sap2-0= ? 001 ? , ? 010 ? , ? 011 ? , ? 100 ? , ? 101 ? ), it is for outputs of negative polar built-in op-amp. connect condenser and stabilize the condition. v8, v20, v43, v55 4 o open test pin. must be left disconnected. vgs 1 i gnd or external resistor this is the standard level of grayscale voltage generator. connect external variable resistor when the level is adjusted for every panel with the source driver. vtest 1 o open test pin. must be left disconnected. ts0-ts7 8 o open test pin. must be left disconnected. test1 1 i gnd or vcc test pin. must be connected at gnd or vcc.
hd66770 rev.1.1 / april 2002 7 figure 2: pad arrangement hd667 a 70 pad arrangement - chip size: 15.06mm x 2.68mm - chip thickness: 55 0um ( typ.) - pad coordinate: pad center - au bump size: (1) 80 um x 80 um dummy1, dummy2, dummy3, dummy4 reset1* to ts7 (2) 30 um x 80um s338 to s59 (3) 80um x 35um s396 to s355, s42 to s1 (4) 45um x 80um s354 to s339, s58 to s43 - au bump pitch: refer to pad coordinate - au bump height: 15 um ( typ.) - number in the diagram refers to number on the pad coordinate. - cross hairs (2) arrangement : 2 places (3) coordinates (x, y) (7151, -1161) (-7151, -1161) - coordinate origin: chip center reset1* to ts7 (1) figure ( straight output arrangement ) 30 40 30 30 40 30 45 45 45 45 190um 190um 95 95 (top view) hd66770 y x 2001.2.28 no.1 no.466 s1 s2 s41 s43 s42 dummy4 s44 16 pins 60ump s60 s59 s339 s340 16 pina 60ump s338 s337 cs* vdh v62p v62n v63p v63n v8 v20 v43 v55 v0 v1p v1n vcom s3 s4 s40 s39 s45 s46 s56 s55 s61 s62 280 pins 45 ? mp s341 s342 v3p v3n v60p v60n test1 vdh vdh s336 s335 dummy1 s57 s58 s354 s353 s352 s351 dummy3 dummy 2 s396 s395 s394 s393 no.110 no.153 42pins 50ump ddvdh ddvdh ddvdh ddvdh ddvdh ddvdh vcc vcc vcc vcc vcc vcc vcc rw/rd* rs osc1 gnddum2 vccdum2 im1 im2 db15 db14 db12 db13 db11 gnddum3 db10 db9 db8 db7 db6 db5 db3 db4 db2 db0/sdi db1/sdo e/wr*/scl gnd gnd gnd gnd gnd gnd gnd gnd gnd osc2 im0/id test 42pins 50ump gnddum1 dcclk reset 1 ?? cl1 flm disptm g gcs* m gcl gda eq vccdum1 reset2 ?? cl1 flm disptmg gcs* dcclk m gcl gda eq vgs vgs vcom ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 s355 s356 s357 s358
hd66770 rev.1.1 / april 2002 8 hd66770pad coordinate (straight) 2001.02.28 rev0.0 no. pad name x y no. pad name x y no. pad name x y no. pad name x y 1 dummy1 -7398 -1208 66 ddvdh 1326 -1208 131 s376 7398 -25 196 s312 5108 1208 2 reset1* -6931 -1208 67 ddvdh 1426 -1208 132 s375 7398 25 197 s311 5063 1208 3 disptmg -6780 -1208 68 vdh 1576 -1208 133 s374 7398 75 198 s310 5018 1208 4 cl1 -6630 -1208 69 vdh 1676 -1208 134 s373 7398 125 199 s309 4973 1208 5 flm -6480 -1208 70 vdh 1776 -1208 135 s372 7398 175 200 s308 4928 1208 6 m -6330 -1208 71 vdh 1877 -1208 136 s371 7398 225 201 s307 4883 1208 7 eq -6180 -1208 72 vgs 2027 -1208 137 s370 7398 275 202 s306 4838 1208 8 gda -6030 -1208 73 vgs 2127 -1208 138 s369 7398 325 203 s305 4793 1208 9 gcs* -5880 -1208 74 v0 2277 -1208 139 s368 7398 375 204 s304 4748 1208 10 gcl -5730 -1208 75 v1p 2427 -1208 140 s367 7398 425 205 s303 4703 1208 11 dcclk -5579 -1208 76 v1n 2577 -1208 141 s366 7398 475 206 s302 4658 1208 12 vccdum1 -5429 -1208 77 v3p 2727 -1208 142 s365 7398 525 207 s301 4613 1208 13 im0/id -5329 -1208 78 v3n 2877 -1208 143 s364 7398 575 208 s300 4568 1208 14 gnddum1 -5229 -1208 79 v60p 3027 -1208 144 s363 7398 626 209 s299 4523 1208 15 im1 -5129 -1208 80 v60n 3178 -1208 145 s362 7398 676 210 s298 4478 1208 16 vccdum2 -5029 -1208 81 v62p 3328 -1208 146 s361 7398 726 211 s297 4433 1208 17 im2 -4929 -1208 82 v62n 3478 -1208 147 s360 7398 776 212 s296 4388 1208 18 gnddum2 -4829 -1208 83 v63p 3628 -1208 148 s359 7398 826 213 s295 4343 1208 19 test -4729 -1208 84 v63n 3778 -1208 149 s358 7398 876 214 s294 4298 1208 20 osc1 -4579 -1208 85 v8 3928 -1208 150 s357 7398 926 215 s293 4253 1208 21 osc2 -4429 -1208 86 v20 4028 -1208 151 s356 7398 976 216 s292 4208 1208 22 db15 -4278 -1208 87 v43 4128 -1208 152 s355 7398 1026 217 s291 4163 1208 23 db14 -4128 -1208 88 v55 4228 -1208 153 dummy3 7398 1208 218 s290 4118 1208 24 db13 -3978 -1208 89 vtest 4328 -1208 154 s354 7232 1208 219 s289 4073 1208 25 db12 -3828 -1208 90 vcom 4479 -1208 155 s353 7172 1208 220 s288 4028 1208 26 db11 -3678 -1208 91 vcom 4579 -1208 156 s352 7112 1208 221 s287 3983 1208 27 db10 -3528 -1208 92 dcclk 4729 -1208 157 s351 7052 1208 222 s286 3938 1208 28 db9 -3378 -1208 93 gcl 4879 -1208 158 s350 6991 1208 223 s285 3893 1208 29 db8 -3228 -1208 94 gcs* 5029 -1208 159 s349 6931 1208 224 s284 3848 1208 30 gnddum3 -3077 -1208 95 gda 5179 -1208 160 s348 6871 1208 225 s283 3803 1208 31 db7 -2927 -1208 96 eq 5329 -1208 161 s347 6811 1208 226 s282 3758 1208 32 db6 -2777 -1208 97 m 5479 -1208 162 s346 6751 1208 227 s281 3713 1208 33 db5 -2627 -1208 98 flm 5630 -1208 163 s345 6691 1208 228 s280 3668 1208 34 db4 -2477 -1208 99 cl1 5780 -1208 164 s344 6631 1208 229 s279 3623 1208 35 db3 -2327 -1208 100 disptmg 5930 -1208 165 s343 6571 1208 230 s278 3578 1208 36 db2 -2177 -1208 101 reset2* 6080 -1208 166 s342 6510 1208 231 s277 3533 1208 37 db1/sdo -2027 -1208 102 ts0 6230 -1208 167 s341 6450 1208 232 s276 3488 1208 38 db0/sdi -1877 -1208 103 ts1 6330 -1208 168 s340 6390 1208 233 s275 3443 1208 39 rw/rd* -1726 -1208 104 ts2 6430 -1208 169 s339 6330 1208 234 s274 3398 1208 40 e/wr*/scl -1576 -1208 105 ts3 6530 -1208 170 s338 6278 1208 235 s273 3353 1208 41 rs -1426 -1208 106 ts4 6630 -1208 171 s337 6233 1208 236 s272 3308 1208 42 cs* -1276 -1208 107 ts5 6730 -1208 172 s336 6188 1208 237 s271 3263 1208 43 test1 -1126 -1208 108 ts6 6830 -1208 173 s335 6143 1208 238 s270 3218 1208 44 gnd -976 -1208 109 ts7 6931 -1208 174 s334 6098 1208 239 s269 3173 1208 45 gnd -876 -1208 110 dummy2 7398 -1208 175 s333 6053 1208 240 s268 3128 1208 46 gnd -776 -1208 111 s396 7398 -1026 176 s332 6008 1208 241 s267 3083 1208 47 gnd -676 -1208 112 s395 7398 -976 177 s331 5963 1208 242 s266 3038 1208 48 gnd -575 -1208 113 s394 7398 -926 178 s330 5918 1208 243 s265 2993 1208 49 gnd -475 -1208 114 s393 7398 -876 179 s329 5873 1208 244 s264 2948 1208 50 gnd -375 -1208 115 s392 7398 -826 180 s328 5828 1208 245 s263 2903 1208 51 gnd -275 -1208 116 s391 7398 -776 181 s327 5783 1208 246 s262 2858 1208 52 gnd -175 -1208 117 s390 7398 -726 182 s326 5738 1208 247 s261 2813 1208 53 gnd -75 -1208 118 s389 7398 -676 183 s325 5693 1208 248 s260 2768 1208 54 vcc 75 -1208 119 s388 7398 -626 184 s324 5648 1208 249 s259 2723 1208 55 vcc 175 -1208 120 s387 7398 -575 185 s323 5603 1208 250 s258 2678 1208 56 vcc 275 -1208 121 s386 7398 -525 186 s322 5558 1208 251 s257 2633 1208 57 vcc 375 -1208 122 s385 7398 -475 187 s321 5513 1208 252 s256 2588 1208 58 vcc 475 -1208 123 s384 7398 -425 188 s320 5468 1208 253 s255 2543 1208 59 vcc 575 -1208 124 s383 7398 -375 189 s319 5423 1208 254 s254 2498 1208 60 vcc 676 -1208 125 s382 7398 -325 190 s318 5378 1208 255 s253 2453 1208 61 ddvdh 826 -1208 126 s381 7398 -275 191 s317 5333 1208 256 s252 2408 1208 62 ddvdh 926 -1208 127 s380 7398 -225 192 s316 5288 1208 257 s251 2363 1208 63 ddvdh 1026 -1208 128 s379 7398 -175 193 s315 5243 1208 258 s250 2318 1208 64 ddvdh 1126 -1208 129 s378 7398 -125 194 s314 5198 1208 259 s249 2273 1208 65 ddvdh 1226 -1208 130 s377 7398 -75 195 s313 5153 1208 260 s248 2228 1208
hd66770 rev.1.1 / april 2002 9 no. pad name x y no. pad name x y no. pad name x y no. pad name x y 261 s247 2183 1208 326 s182 -743 1208 391 s117 -3668 1208 456 s52 -6691 1208 262 s246 2138 1208 327 s181 -788 1208 392 s116 -3713 1208 457 s51 -6751 1208 263 s245 2093 1208 328 s180 -833 1208 393 s115 -3758 1208 458 s50 -6811 1208 264 s244 2048 1208 329 s179 -878 1208 394 s114 -3803 1208 459 s49 -6871 1208 265 s243 2003 1208 330 s178 -923 1208 395 s113 -3848 1208 460 s48 -6931 1208 266 s242 1958 1208 331 s177 -968 1208 396 s112 -3893 1208 461 s47 -6991 1208 267 s241 1913 1208 332 s176 -1013 1208 397 s111 -3938 1208 462 s46 -7052 1208 268 s240 1868 1208 333 s175 -1058 1208 398 s110 -3983 1208 463 s45 -7112 1208 269 s239 1823 1208 334 s174 -1103 1208 399 s109 -4028 1208 464 s44 -7172 1208 270 s238 1778 1208 335 s173 -1148 1208 400 s108 -4073 1208 465 s43 -7232 1208 271 s237 1733 1208 336 s172 -1193 1208 401 s107 -4118 1208 466 dummy4 -7398 1208 272 s236 1688 1208 337 s171 -1238 1208 402 s106 -4163 1208 467 s42 -7398 1026 273 s235 1643 1208 338 s170 -1283 1208 403 s105 -4208 1208 468 s41 -7398 976 274 s234 1598 1208 339 s169 -1328 1208 404 s104 -4253 1208 469 s40 -7398 926 275 s233 1553 1208 340 s168 -1373 1208 405 s103 -4298 1208 470 s39 -7398 876 276 s232 1508 1208 341 s167 -1418 1208 406 s102 -4343 1208 471 s38 -7398 826 277 s231 1463 1208 342 s166 -1463 1208 407 s101 -4388 1208 472 s37 -7398 776 278 s230 1418 1208 343 s165 -1508 1208 408 s100 -4433 1208 473 s36 -7398 726 279 s229 1373 1208 344 s164 -1553 1208 409 s99 -4478 1208 474 s35 -7398 676 280 s228 1328 1208 345 s163 -1598 1208 410 s98 -4523 1208 475 s34 -7398 626 281 s227 1283 1208 346 s162 -1643 1208 411 s97 -4568 1208 476 s33 -7398 575 282 s226 1238 1208 347 s161 -1688 1208 412 s96 -4613 1208 477 s32 -7398 525 283 s225 1193 1208 348 s160 -1733 1208 413 s95 -4658 1208 478 s31 -7398 475 284 s224 1148 1208 349 s159 -1778 1208 414 s94 -4703 1208 479 s30 -7398 425 285 s223 1103 1208 350 s158 -1823 1208 415 s93 -4748 1208 480 s29 -7398 375 286 s222 1058 1208 351 s157 -1868 1208 416 s92 -4793 1208 481 s28 -7398 325 287 s221 1013 1208 352 s156 -1913 1208 417 s91 -4838 1208 482 s27 -7398 275 288 s220 968 1208 353 s155 -1958 1208 418 s90 -4883 1208 483 s26 -7398 225 289 s219 923 1208 354 s154 -2003 1208 419 s89 -4928 1208 484 s25 -7398 175 290 s218 878 1208 355 s153 -2048 1208 420 s88 -4973 1208 485 s24 -7398 125 291 s217 833 1208 356 s152 -2093 1208 421 s87 -5018 1208 486 s23 -7398 75 292 s216 788 1208 357 s151 -2138 1208 422 s86 -5063 1208 487 s22 -7398 25 293 s215 743 1208 358 s150 -2183 1208 423 s85 -5108 1208 488 s21 -7398 -25 294 s214 698 1208 359 s149 -2228 1208 424 s84 -5153 1208 489 s20 -7398 -75 295 s213 653 1208 360 s148 -2273 1208 425 s83 -5198 1208 490 s19 -7398 -125 296 s212 608 1208 361 s147 -2318 1208 426 s82 -5243 1208 491 s18 -7398 -175 297 s211 563 1208 362 s146 -2363 1208 427 s81 -5288 1208 492 s17 -7398 -225 298 s210 518 1208 363 s145 -2408 1208 428 s80 -5333 1208 493 s16 -7398 -275 299 s209 473 1208 364 s144 -2453 1208 429 s79 -5378 1208 494 s15 -7398 -325 300 s208 428 1208 365 s143 -2498 1208 430 s78 -5423 1208 495 s14 -7398 -375 301 s207 383 1208 366 s142 -2543 1208 431 s77 -5468 1208 496 s13 -7398 -425 302 s206 338 1208 367 s141 -2588 1208 432 s76 -5513 1208 497 s12 -7398 -475 303 s205 293 1208 368 s140 -2633 1208 433 s75 -5558 1208 498 s11 -7398 -525 304 s204 248 1208 369 s139 -2678 1208 434 s74 -5603 1208 499 s10 -7398 -575 305 s203 203 1208 370 s138 -2723 1208 435 s73 -5648 1208 500 s9 -7398 -626 306 s202 158 1208 371 s137 -2768 1208 436 s72 -5693 1208 501 s8 -7398 -676 307 s201 113 1208 372 s136 -2813 1208 437 s71 -5738 1208 502 s7 -7398 -726 308 s200 68 1208 373 s135 -2858 1208 438 s70 -5783 1208 503 s6 -7398 -776 309 s199 23 1208 374 s134 -2903 1208 439 s69 -5828 1208 504 s5 -7398 -826 310 s198 -23 1208 375 s133 -2948 1208 440 s68 -5873 1208 505 s4 -7398 -876 311 s197 -68 1208 376 s132 -2993 1208 441 s67 -5918 1208 506 s3 -7398 -926 312 s196 -113 1208 377 s131 -3038 1208 442 s66 -5963 1208 507 s2 -7398 -976 313 s195 -158 1208 378 s130 -3083 1208 443 s65 -6008 1208 508 s1 -7398 -1026 314 s194 -203 1208 379 s129 -3128 1208 444 s64 -6053 1208 315 s193 -248 1208 380 s128 -3173 1208 445 s63 -6098 1208 cross hairs -7151 -1161 316 s192 -293 1208 381 s127 -3218 1208 446 s62 -6143 1208 7151 -1161 317 s191 -338 1208 382 s126 -3263 1208 447 s61 -6188 1208 318 s190 -383 1208 383 s125 -3308 1208 448 s60 -6233 1208 319 s189 -428 1208 384 s124 -3353 1208 449 s59 -6278 1208 320 s188 -473 1208 385 s123 -3398 1208 450 s58 -6330 1208 321 s187 -518 1208 386 s122 -3443 1208 451 s57 -6390 1208 322 s186 -563 1208 387 s121 -3488 1208 452 s56 -6450 1208 323 s185 -608 1208 388 s120 -3533 1208 453 s55 -6510 1208 324 s184 -653 1208 389 s119 -3578 1208 454 s54 -6571 1208 325 s183 -698 1208 390 s118 -3623 1208 455 s53 -6631 1208 hd66770 pad coordinate (straight)
hd66770 rev.1.1 / april 2002 10 - chip size: 15.06mm x 2.68mm - chip thickness: 55 0um ( typ.) - pad coordinate: pad center - au bump size: (1) 80 um x 80 um dummy1, dummy2, dummy3, dummy4 reset1* to ts7 (2) 30 um x 80um s338 to s59 (3) 80um x 35um s396 to s355, s42 to s1 (4) 45um x 80um s354 to s339, s58 to s43 - au bump pitch: refer to pad coordinate - au bump height: 15 um ( typ.) - number in the diagram refers to number on the pad coordinate. - cross hairs (2) arrangement : 2 places (3) coordinates (x, y) (7151, -1161) (-7151, -1161) hd667 b 70 pad arrangement - coordinate origin: chip center reset1* to ts7 (1) figure ( laced output arrangement ) 30 40 30 30 40 30 45 45 45 45 190um 190um 95 95 (top view) hd66770 y x 2001.2.28 no.1 no.466 s1 s2 s41 s43 s42 dummy4 s44 16 pins 60ump s60 s59 s339 s340 16 pina 60ump s338 s337 cs* vdh v62p v62n v63p v63n v8 v20 v43 v55 v0 v1p v1n vcom s3 s4 s40 s39 s45 s46 s56 s55 s61 s62 280 pins 45 ? mp s341 s342 v3p v3n v60p v60n test1 vdh vdh s336 s335 dummy1 s57 s58 s354 s353 s352 s351 dummy3 dummy 2 s396 s395 s394 s393 no.110 no.153 42pins 50ump ddvdh ddvdh ddvdh ddvdh ddvdh ddvdh gnd vcc vcc vcc vcc vcc vcc vcc rw/rd* rs osc1 gnddum2 vccdum2 im1 im2 db15 db14 db12 db13 db11 gnddum3 db10 db9 db8 db7 db6 db5 db3 db4 db2 db0/sdi db1/sdo e/wr*/scl gnd gnd gnd gnd gnd gnd gnd gnd gnd osc2 im0/id test 42pins 50ump gnddum1 dcclk reset 1 ?? cl1 flm disptm g gcs* m gcl gda eq vccdum1 reset2 ?? cl1 flm disptmg gcs* dcclk m gcl gda eq vgs vgs vcom ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 s355 s356 s357 s358 figure 3: pad arrangement
hd66770 rev.1.1 / april 2002 11 hd66770 pad coordinate ?i laced coordinate ?j 2001.2.28 rev0.0 no. padname x y no. padname x y no. padname x y no. padname x y 1 dummy1 -7398 -1208 66 ddvdh 1326 -1208 131 s376 7283 -25 196 s312 5108 1093 2 reset1* -6931 -1208 67 ddvdh 1426 -1208 132 s375 7398 25 197 s311 5063 1208 3 disptmg -6780 -1208 68 vdh 1576 -1208 133 s374 7283 75 198 s310 5018 1093 4 cl1 -6630 -1208 69 vdh 1676 -1208 134 s373 7398 125 199 s309 4973 1208 5 flm -6480 -1208 70 vdh 1776 -1208 135 s372 7283 175 200 s308 4928 1093 6 m -6330 -1208 71 vdh 1877 -1208 136 s371 7398 225 201 s307 4883 1208 7 eq -6180 -1208 72 vgs 2027 -1208 137 s370 7283 275 202 s306 4838 1093 8 gda -6030 -1208 73 vgs 2127 -1208 138 s369 7398 325 203 s305 4793 1208 9 gcs* -5880 -1208 74 v0 2277 -1208 139 s368 7283 375 204 s304 4748 1093 10 gcl -5730 -1208 75 v1p 2427 -1208 140 s367 7398 425 205 s303 4703 1208 11 dcclk -5579 -1208 76 v1n 2577 -1208 141 s366 7283 475 206 s302 4658 1093 12 vccdum1 -5429 -1208 77 v3p 2727 -1208 142 s365 7398 525 207 s301 4613 1208 13 im0/id -5329 -1208 78 v3n 2877 -1208 143 s364 7283 575 208 s300 4568 1093 14 gnddum1 -5229 -1208 79 v60p 3027 -1208 144 s363 7398 626 209 s299 4523 1208 15 im1 -5129 -1208 80 v60n 3178 -1208 145 s362 7283 676 210 s298 4478 1093 16 vccdum2 -5029 -1208 81 v62p 3328 -1208 146 s361 7398 726 211 s297 4433 1208 17 im2 -4929 -1208 82 v62n 3478 -1208 147 s360 7283 776 212 s296 4388 1093 18 gnddum2 -4829 -1208 83 v63p 3628 -1208 148 s359 7398 826 213 s295 4343 1208 19 test -4729 -1208 84 v63n 3778 -1208 149 s358 7283 876 214 s294 4298 1093 20 osc1 -4579 -1208 85 v8 3928 -1208 150 s357 7398 926 215 s293 4253 1208 21 osc2 -4429 -1208 86 v20 4028 -1208 151 s356 7283 976 216 s292 4208 1093 22 db15 -4278 -1208 87 v43 4128 -1208 152 s355 7398 1026 217 s291 4163 1208 23 db14 -4128 -1208 88 v55 4228 -1208 153 dummy3 7398 1208 218 s290 4118 1093 24 db13 -3978 -1208 89 vtest 4328 -1208 154 s354 7232 1093 219 s289 4073 1208 25 db12 -3828 -1208 90 vcom 4479 -1208 155 s353 7172 1208 220 s288 4028 1093 26 db11 -3678 -1208 91 vcom 4579 -1208 156 s352 7112 1093 221 s287 3983 1208 27 db10 -3528 -1208 92 dcclk 4729 -1208 157 s351 7052 1208 222 s286 3938 1093 28 db9 -3378 -1208 93 gcl 4879 -1208 158 s350 6991 1093 223 s285 3893 1208 29 db8 -3228 -1208 94 gcs* 5029 -1208 159 s349 6931 1208 224 s284 3848 1093 30 gnddum3 -3077 -1208 95 gda 5179 -1208 160 s348 6871 1093 225 s283 3803 1208 31 db7 -2927 -1208 96 eq 5329 -1208 161 s347 6811 1208 226 s282 3758 1093 32 db6 -2777 -1208 97 m 5479 -1208 162 s346 6751 1093 227 s281 3713 1208 33 db5 -2627 -1208 98 flm 5630 -1208 163 s345 6691 1208 228 s280 3668 1093 34 db4 -2477 -1208 99 cl1 5780 -1208 164 s344 6631 1093 229 s279 3623 1208 35 db3 -2327 -1208 100 disptmg 5930 -1208 165 s343 6571 1208 230 s278 3578 1093 36 db2 -2177 -1208 101 reset2* 6080 -1208 166 s342 6510 1093 231 s277 3533 1208 37 db1/sdo -2027 -1208 102 ts0 6230 -1208 167 s341 6450 1208 232 s276 3488 1093 38 db0/sdi -1877 -1208 103 ts1 6330 -1208 168 s340 6390 1093 233 s275 3443 1208 39 rw/rd* -1726 -1208 104 ts2 6430 -1208 169 s339 6330 1208 234 s274 3398 1093 40 e/wr*/scl -1576 -1208 105 ts3 6530 -1208 170 s338 6278 1093 235 s273 3353 1208 41 rs -1426 -1208 106 ts4 6630 -1208 171 s337 6233 1208 236 s272 3308 1093 42 cs* -1276 -1208 107 ts5 6730 -1208 172 s336 6188 1093 237 s271 3263 1208 43 test1 -1126 -1208 108 ts6 6830 -1208 173 s335 6143 1208 238 s270 3218 1093 44 gnd -976 -1208 109 ts7 6931 -1208 174 s334 6098 1093 239 s269 3173 1208 45 gnd -876 -1208 110 dummy2 7398 -1208 175 s333 6053 1208 240 s268 3128 1093 46 gnd -776 -1208 111 s396 7283 -1026 176 s332 6008 1093 241 s267 3083 1208 47 gnd -676 -1208 112 s395 7398 -976 177 s331 5963 1208 242 s266 3038 1093 48 gnd -575 -1208 113 s394 7283 -926 178 s330 5918 1093 243 s265 2993 1208 49 gnd -475 -1208 114 s393 7398 -876 179 s329 5873 1208 244 s264 2948 1093 50 gnd -375 -1208 115 s392 7283 -826 180 s328 5828 1093 245 s263 2903 1208 51 gnd -275 -1208 116 s391 7398 -776 181 s327 5783 1208 246 s262 2858 1093 52 gnd -175 -1208 117 s390 7283 -726 182 s326 5738 1093 247 s261 2813 1208 53 gnd -75 -1208 118 s389 7398 -676 183 s325 5693 1208 248 s260 2768 1093 54 vcc 75 -1208 119 s388 7283 -626 184 s324 5648 1093 249 s259 2723 1208 55 vcc 175 -1208 120 s387 7398 -575 185 s323 5603 1208 250 s258 2678 1093 56 vcc 275 -1208 121 s386 7283 -525 186 s322 5558 1093 251 s257 2633 1208 57 vcc 375 -1208 122 s385 7398 -475 187 s321 5513 1208 252 s256 2588 1093 58 vcc 475 -1208 123 s384 7283 -425 188 s320 5468 1093 253 s255 2543 1208 59 vcc 575 -1208 124 s383 7398 -375 189 s319 5423 1208 254 s254 2498 1093 60 vcc 676 -1208 125 s382 7283 -325 190 s318 5378 1093 255 s253 2453 1208 61 ddvdh 826 -1208 126 s381 7398 -275 191 s317 5333 1208 256 s252 2408 1093 62 ddvdh 926 -1208 127 s380 7283 -225 192 s316 5288 1093 257 s251 2363 1208 63 ddvdh 1026 -1208 128 s379 7398 -175 193 s315 5243 1208 258 s250 2318 1093 64 ddvdh 1126 -1208 129 s378 7283 -125 194 s314 5198 1093 259 s249 2273 1208 65 ddvdh 1226 -1208 130 s377 7398 -75 195 s313 5153 1208 260 s248 2228 1093
hd66770 rev.1.1 / april 2002 12 hd66770 pad coordinate ?i laced coordinate ?j no. padname x y no. padname x y no. padname x y no. padname x y 261 s247 2183 1208 326 s182 -743 1093 391 s117 -3668 1208 456 s52 -6691 1093 262 s246 2138 1093 327 s181 -788 1208 392 s116 -3713 1093 457 s51 -6751 1208 263 s245 2093 1208 328 s180 -833 1093 393 s115 -3758 1208 458 s50 -6811 1093 264 s244 2048 1093 329 s179 -878 1208 394 s114 -3803 1093 459 s49 -6871 1208 265 s243 2003 1208 330 s178 -923 1093 395 s113 -3848 1208 460 s48 -6931 1093 266 s242 1958 1093 331 s177 -968 1208 396 s112 -3893 1093 461 s47 -6991 1208 267 s241 1913 1208 332 s176 -1013 1093 397 s111 -3938 1208 462 s46 -7052 1093 268 s240 1868 1093 333 s175 -1058 1208 398 s110 -3983 1093 463 s45 -7112 1208 269 s239 1823 1208 334 s174 -1103 1093 399 s109 -4028 1208 464 s44 -7172 1093 270 s238 1778 1093 335 s173 -1148 1208 400 s108 -4073 1093 465 s43 -7232 1208 271 s237 1733 1208 336 s172 -1193 1093 401 s107 -4118 1208 466 dummy4 -7398 1208 272 s236 1688 1093 337 s171 -1238 1208 402 s106 -4163 1093 467 s42 -7283 1026 273 s235 1643 1208 338 s170 -1283 1093 403 s105 -4208 1208 468 s41 -7398 976 274 s234 1598 1093 339 s169 -1328 1208 404 s104 -4253 1093 469 s40 -7283 926 275 s233 1553 1208 340 s168 -1373 1093 405 s103 -4298 1208 470 s39 -7398 876 276 s232 1508 1093 341 s167 -1418 1208 406 s102 -4343 1093 471 s38 -7283 826 277 s231 1463 1208 342 s166 -1463 1093 407 s101 -4388 1208 472 s37 -7398 776 278 s230 1418 1093 343 s165 -1508 1208 408 s100 -4433 1093 473 s36 -7283 726 279 s229 1373 1208 344 s164 -1553 1093 409 s99 -4478 1208 474 s35 -7398 676 280 s228 1328 1093 345 s163 -1598 1208 410 s98 -4523 1093 475 s34 -7283 626 281 s227 1283 1208 346 s162 -1643 1093 411 s97 -4568 1208 476 s33 -7398 575 282 s226 1238 1093 347 s161 -1688 1208 412 s96 -4613 1093 477 s32 -7283 525 283 s225 1193 1208 348 s160 -1733 1093 413 s95 -4658 1208 478 s31 -7398 475 284 s224 1148 1093 349 s159 -1778 1208 414 s94 -4703 1093 479 s30 -7283 425 285 s223 1103 1208 350 s158 -1823 1093 415 s93 -4748 1208 480 s29 -7398 375 286 s222 1058 1093 351 s157 -1868 1208 416 s92 -4793 1093 481 s28 -7283 325 287 s221 1013 1208 352 s156 -1913 1093 417 s91 -4838 1208 482 s27 -7398 275 288 s220 968 1093 353 s155 -1958 1208 418 s90 -4883 1093 483 s26 -7283 225 289 s219 923 1208 354 s154 -2003 1093 419 s89 -4928 1208 484 s25 -7398 175 290 s218 878 1093 355 s153 -2048 1208 420 s88 -4973 1093 485 s24 -7283 125 291 s217 833 1208 356 s152 -2093 1093 421 s87 -5018 1208 486 s23 -7398 75 292 s216 788 1093 357 s151 -2138 1208 422 s86 -5063 1093 487 s22 -7283 25 293 s215 743 1208 358 s150 -2183 1093 423 s85 -5108 1208 488 s21 -7398 -25 294 s214 698 1093 359 s149 -2228 1208 424 s84 -5153 1093 489 s20 -7283 -75 295 s213 653 1208 360 s148 -2273 1093 425 s83 -5198 1208 490 s19 -7398 -125 296 s212 608 1093 361 s147 -2318 1208 426 s82 -5243 1093 491 s18 -7283 -175 297 s211 563 1208 362 s146 -2363 1093 427 s81 -5288 1208 492 s17 -7398 -225 298 s210 518 1093 363 s145 -2408 1208 428 s80 -5333 1093 493 s16 -7283 -275 299 s209 473 1208 364 s144 -2453 1093 429 s79 -5378 1208 494 s15 -7398 -325 300 s208 428 1093 365 s143 -2498 1208 430 s78 -5423 1093 495 s14 -7283 -375 301 s207 383 1208 366 s142 -2543 1093 431 s77 -5468 1208 496 s13 -7398 -425 302 s206 338 1093 367 s141 -2588 1208 432 s76 -5513 1093 497 s12 -7283 -475 303 s205 293 1208 368 s140 -2633 1093 433 s75 -5558 1208 498 s11 -7398 -525 304 s204 248 1093 369 s139 -2678 1208 434 s74 -5603 1093 499 s10 -7283 -575 305 s203 203 1208 370 s138 -2723 1093 435 s73 -5648 1208 500 s9 -7398 -626 306 s202 158 1093 371 s137 -2768 1208 436 s72 -5693 1093 501 s8 -7283 -676 307 s201 113 1208 372 s136 -2813 1093 437 s71 -5738 1208 502 s7 -7398 -726 308 s200 68 1093 373 s135 -2858 1208 438 s70 -5783 1093 503 s6 -7283 -776 309 s199 23 1208 374 s134 -2903 1093 439 s69 -5828 1208 504 s5 -7398 -826 310 s198 -23 1093 375 s133 -2948 1208 440 s68 -5873 1093 505 s4 -7283 -876 311 s197 -68 1208 376 s132 -2993 1093 441 s67 -5918 1208 506 s3 -7398 -926 312 s196 -113 1093 377 s131 -3038 1208 442 s66 -5963 1093 507 s2 -7283 -976 313 s195 -158 1208 378 s130 -3083 1093 443 s65 -6008 1208 508 s1 -7398 -1026 314 s194 -203 1093 379 s129 -3128 1208 444 s64 -6053 1093 315 s193 -248 1208 380 s128 -3173 1093 445 s63 -6098 1208 cross hairs -7151 -1161 316 s192 -293 1093 381 s127 -3218 1208 446 s62 -6143 1093 7151 -1161 317 s191 -338 1208 382 s126 -3263 1093 447 s61 -6188 1208 318 s190 -383 1093 383 s125 -3308 1208 448 s60 -6233 1093 319 s189 -428 1208 384 s124 -3353 1093 449 s59 -6278 1208 320 s188 -473 1093 385 s123 -3398 1208 450 s58 -6330 1093 321 s187 -518 1208 386 s122 -3443 1093 451 s57 -6390 1208 322 s186 -563 1093 387 s121 -3488 1208 452 s56 -6450 1093 323 s185 -608 1208 388 s120 -3533 1093 453 s55 -6510 1208 324 s184 -653 1093 389 s119 -3578 1208 454 s54 -6571 1093 325 s183 -698 1208 390 s118 -3623 1093 455 s53 -6631 1208
hd66770 rev.1. 1 / april 2002 13 block function description system interface the hd66770 has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8- bit bus, and a serial peripheral (spi: serial peripheral interface port ). the interface mode is selected by the im2-0 pins. the hd66770 has three 16-bit registers: an index register (ir), a write data register (wdr), and a read data register (rdr). the ir stores index information from the control registers and the gram. the wdr temporarily stores data to be written into control registers and the gram, and the rdr temporarily stores data read from the gram. data written into the gram from the mpu is first written into the wdr and then is automatically written into the gram by internal operation. data is read through the rdr when reading from the gram, and the first read data is invalid and the second and the following data are normal. when a logic operation is performed inside of the hd66770 by using the display data set in the gram and the data written from the mpu, the data read through the rdr is used. accordingly, the mpu does not need to read data twice nor to fetch the read data into the mpu. this enables high-speed processing. execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written in succession. table 2 register selection (8/16 parallel interface) 80-system bus 68-system bus wr * rd * r/w rs operations 0 1 0 0 writes indexes into ir 1 0 1 0 reads internal status 0 1 0 1 writes into control registers and gram through wdr 1 0 1 1 reads from gram through rdr table 3 register selection (serial peripheral interface) start bytes r/w bits rs bits operations 0 0 writes indexes into ir 1 0 reads internal status 0 1 writes into control registers and gram through wdr 1 1 reads from gram through rdr bit operation the hd66770 supports the following functions: a write data mask function that selects and writes data into the gram in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the gram and writes into the gram. with the 16-bit bus interface, these functions can greatly reduce the processing loads of the mpu graphics software and can rewrite the display data in the gram at high speed. for details, see the graphics operation function section.
hd66770 rev.1. 1 / april 2002 14 address counter (ac) the address counter (ac) assigns address to the gram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. after writing into the gram, the ac is automatically incremented by 1 (or decremented by 1). after reading from the data, the ac is not updated. a window address function allows for data to be written only to a window area specified by gram. graphics ram (gram) the graphics ram (gram) has 16 bits/pixel and stores the bit-pattern data of 132 x 176 bytes. grayscale voltage generator the grayscale voltage circuit generates a lcd driver circuit that corresponds to the grayscale level s as specified in the grayscale gamma-adjusting re sis t or. 65 ,536 possible colors can be displayed at the same time. for details, see the gamma- adjusting resistor. timing generator the timing generator generates timing signals for the operation of internal circuits such as the gram. the ram read timing for display and internal operation timing by mpu access are generated separately to avoid interference with one another. the timing generator generates the interface signals (m, flm, cl1, eq, dcclk , disptmg ) for the gate driver and the power supply ic . oscillation circuit (osc) the hd66770 can provide r-c oscillation simply through the addition of an external oscillation-resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can also be supplied externally. since r-c oscillation stops during the standby mode, current consumption can be reduced. for details, see the oscillation circuit section. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 396 source drivers (s1 to s 396 ). display pattern data is latched when 396 -bit data has arrived. the latched data then enables the source drivers to generate drive waveform outputs. the shift direction of 396 -bit data can be changed by the ss bit by select ing an appropriate direction for the device-mounting configuration. interface with gate driver a serial int e rface circuit provides an interface with the hd66771 and hd667p00. when sending an instruction setting from the hd66770 to the hd66771 and hd667p00 , a register setting value from within the hd66770 is transferred via the serial interface circuit. a transfer is started by setting a serial transfer enable of the hd667 70 . however, transfer to and reading from the hd66771 or hd667p00 is not possible during standby. for details, see the gate serial transfer section
hd66770 rev.1. 1 / april 2002 15 table 4: relationship between gram address and display position (ss = ? 0 ? ) table 5: relationship between gram address and output pin s385 s386 s387 s388 s389 s390 db 11 db 0 db 11 db 0 s391 s392 s393 s394 s395 s396 db 11 db 0 db 11 db 0 s7 s8 s9 s10 s11 s12 db 11 db 0 db 11 db 0 g176 s1 s2 s3 s4 s5 s6 g175 g174 g173 g172 g171 g170 g169 g168 g167 g166 g165 g164 g163 g162 g161 g160 g159 g158 g157 g7 g6 g5 g8 g4 g3 g2 g1 db 11 db 0 db 11 db 0 "0001"h "0101"h "0201"h "0301"h "0401"h "0501 h "0601"h "0701"h "0801"h "0901"h "0a01"h "0b01"h "0c01"h "0d01"h "0e01"h "0f01"h "1001"h "1101"h "1201"h "1301"h "a801"h "a901"h "aa01"h "ab01"h "ac01"h "ad01"h "ae01"h "af01"h "0000"h "0100"h "0200"h "0300"h "0400"h "0500"h "0600"h "0700"h "0800"h "0900"h "0a00"h "0b00"h "0c00"h "0d00"h "0e00"h "0f00"h "1000"h "1100"h "1200"h "1300"h "a800"h "a900"h "aa00"h "ab00"h "ac00"h "ad00"h "ae00"h "af00"h g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 g15 g16 g17 g18 g19 g20 g170 g171 g172 g169 g173 g174 g175 g176 gs=1 gs=0 s/g pin "0002"h "0102"h "0202"h "0302"h "0402"h "0502"h "0602"h "0702"h "0802"h "0902"h "0a02"h "0b02"h "0c02"h "0d02"h "0e02"h "0f02"h "1002"h "1102"h "1202"h "1302"h "a802"h "a902"h "aa02"h "ab02"h "ac02"h "ad02"h "ae02"h "af02"h "0003"h "0103"h "0203"h "0303"h "0403"h "0503"h "0603"h "0703"h "0803"h "0903"h "0a03"h "0b03"h "0c03"h "0d03"h "0e03"h "0f03"h "1003"h "1103"h "1203"h "1303"h "a803"h "a903"h "aa03"h "ab03"h "ac03"h "ad03"h "ae03"h "af03"h "0081"h "0181"h "0281"h "0381"h "0481"h "0581 h "0681"h "0781"h "0881"h "0981"h "0a81"h "0b81"h "0c81"h "0d81"h "0e81"h "0f81"h "1081"h "1181"h "1281"h "1381"h "a881"h "a981"h "aa81"h "ab81"h "ac81"h "ad81"h "ae81"h "af81"h "0080"h "0180"h "0280"h "0380"h "0480"h "0580"h "0680"h "0780"h "0880"h "0980"h "0a80"h "0b80"h "0c80"h "0d80"h "0e80"h "0f80"h "1080"h "1180"h "1280"h "1380"h "a880"h "a980"h "aa80"h "ab80"h "ac80"h "ad80"h "ae80"h "af80"h "0082"h "0182"h "0282"h "0382"h "0482"h "0582"h "0682"h "0782"h "0882"h "0982"h "0a82"h "0b82"h "0c82"h "0d82"h "0e82"h "0f82"h "1082"h "1182"h "1282"h "1382"h "a882"h "a982"h "aa82"h "ab82"h "ac82"h "ad82"h "ae82"h "af82"h "0083"h "0183"h "0283"h "0383"h "0483"h "0583"h "0683"h "0783"h "0883"h "0983"h "0a83"h "0b83"h "0c83"h "0d83"h "0e83"h "0f83"h "1083"h "1183"h "1283"h "1383"h "a883"h "a983"h "aa83"h "ab83"h "ac83"h "ad83"h "ae83"h "af83"h db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 r g b s(3n+1) s(3n+3) gram data rgb allotment output pin
hd66770 rev.1. 1 / april 2002 16 table 6: relationship between gram address and display position (ss = ? 1 ? ) table 7: relationship between gram address and output pin s385 s386 s387 s388 s389 s390 db 0 db 11 db 0 db 11 s391 s392 s393 s394 s395 s396 db 0 db 11 db 0 db 11 s7 s8 s9 s10 s11 s12 db 0 db 11 db 0 db 11 g176 s1 s2 s3 s4 s5 s6 g175 g174 g173 g172 g171 g170 g169 g168 g167 g166 g165 g164 g163 g162 g161 g160 g159 g158 g157 g7 g6 g5 g8 g4 g3 g2 g1 db 0 db 11 db 0 db 11 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 g15 g16 g17 g18 g19 g20 g170 g171 g172 g169 g173 g174 g175 g176 gs=1 gs=0 s/g pin "0083"h "0183"h "0283"h "0383"h "0483"h "0583"h "0683"h "0783"h "0883"h "0983"h "0a83"h "0b83"h "0c83"h "0d83"h "0e83"h "0f83"h "1083"h "1183"h "1283"h "1383"h "a883"h "a983"h "aa83"h "ab83"h "ac83"h "ad83"h "ae83"h "af83"h "0082"h "0182"h "0282"h "0382"h "0482"h "0582"h "0682"h "0782"h "0882"h "0982"h "0a82"h "0b82"h "0c82"h "0d82"h "0e82"h "0f82"h "1082"h "1182"h "1282"h "1382"h "a882"h "a982"h "aa82"h "ab82"h "ac82"h "ad82"h "ae82"h "af82"h "0081"h "0181"h "0281"h "0381"h "0481"h "0581 h "0681"h "0781"h "0881"h "0981"h "0a81"h "0b81"h "0c81"h "0d81"h "0e81"h "0f81"h "1081"h "1181"h "1281"h "1381"h "a881"h "a981"h "aa81"h "ab81"h "ac81"h "ad81"h "ae81"h "af81"h "0080"h "0180"h "0280"h "0380"h "0480"h "0580"h "0680"h "0780"h "0880"h "0980"h "0a80"h "0b80"h "0c80"h "0d80"h "0e80"h "0f80"h "1080"h "1180"h "1280"h "1380"h "a880"h "a980"h "aa80"h "ab80"h "ac80"h "ad80"h "ae80"h "af80"h "0003"h "0103"h "0203"h "0303"h "0403"h "0503"h "0603"h "0703"h "0803"h "0903"h "0a03"h "0b03"h "0c03"h "0d03"h "0e03"h "0f03"h "1003"h "1103"h "1203"h "1303"h "a803"h "a903"h "aa03"h "ab03"h "ac03"h "ad03"h "ae03"h "af03"h "0002"h "0102"h "0202"h "0302"h "0402"h "0502"h "0602"h "0702"h "0802"h "0902"h "0a02"h "0b02"h "0c02"h "0d02"h "0e02"h "0f02"h "1002"h "1102"h "1202"h "1302"h "a802"h "a902"h "aa02"h "ab02"h "ac02"h "ad02"h "ae02"h "af02"h "0001"h "0101"h "0201"h "0301"h "0401"h "0501 h "0601"h "0701"h "0801"h "0901"h "0a01"h "0b01"h "0c01"h "0d01"h "0e01"h "0f01"h "1001"h "1101"h "1201"h "1301"h "a801"h "a901"h "aa01"h "ab01"h "ac01"h "ad01"h "ae01"h "af01"h "0000"h "0100"h "0200"h "0300"h "0400"h "0500"h "0600"h "0700"h "0800"h "0900"h "0a00"h "0b00"h "0c00"h "0d00"h "0e00"h "0f00"h "1000"h "1100"h "1200"h "1300"h "a800"h "a900"h "aa00"h "ab00"h "ac00"h "ad00"h "ae00"h "af00"h db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 gram data output pin s(396-3n) s(395-3n) s(394-3n) r g b rgb allotment
hd66770 rev.1. 1 / april 2002 17 instructions outline the hd66770 uses the 16-bit bus architecture. before the internal operation of the hd66770 starts, control information is temporarily stored in the registers described below to allow high- speed interfacing with a high-performance microcomputer. the internal operation of the hd66770 is determined by signals sent from the microcomputer. these signals, which include the register selection signal (rs), the read/write signal (r/w), and the data bus signals (db15 to db0), make up the hd66770 instructions. there are nine categories of instructions that: specify the index read the status control the display control power management process the graphics data set internal gram addresses transfer data to and from the internal gram set grayscale level for the internal grayscale gamma adjustment interface with the gate driver and power supply ic normally, instructions that write data are used the most. however, an auto-update of internal gram addresses after each data write can lighten the microcomputer program load. because instructions are executed in 0 cycles, they can be written in succession.
hd66770 rev.1. 1 / april 2002 18 in struction descriptions index the index instruction specifies the ram control indexes (r00h to r3fh). it sets the register number in the range of 00000 to 11 1111 in binary form. however, r40 to r44 are disabled since they are test registers. figure 4 index instruction s tatus read the status read instruction reads the internal status of the hd66770. l7 ? 0: indicate the driving raster-row position where the liquid crystal display is being driven. figure 5 status read instruction start oscillation (r00h) the start oscillation instruction restarts the oscillator from the halt state in the standby mode. after issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (see the standby mode section.) if this register is read forcibly, * 0 770h is read. figure 6 start oscillation instruction driver output control (r01h) figure 7 driver output control instruction gs: selects the output shift direction of the gate driver. when gs = 0, g1 shifts to g228 . when g s = 1, g228 shifts to g 1 w 0 * * * * * * * * id6 id4 id3 id2 id1 id0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 * id5 r 0 l6 l5 l4 l3 l2 l1 l0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 l7 0 0 0 0 0 0 0 0 w 1 * * * * * * * 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 * * * * * * * * r 1 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 w 1 gs ss r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 nl0 nl1 nl2 nl3 0 0 0 0 0 0 0 0 0 nl4
hd66770 rev.1. 1 / april 2002 19 ss: selects the output shift direction of the source driver . when ss = 0, s1 shifts to s396 . when ss = 1, s396 shifts to s1 . when ss = 0, color is assigned from s1. when ss = 1 , color is assigned from s 396 . re-write to the ram when intending to change the ss bit. note: the gs bit is for setting the gate driver . control according to the bit ? s value is executed by the gate driver. for details, see the data sheet for the gate driver . nl4 ? 0: specify number of lines for the lcd drive. number of lines for the lcd drive can be adjusted for every eight raster-rows. gram address mapping does not depend on the setting value of the drive duty ratio. select the set value for the panel size or higher. t able 8: nl bits and drive duty note: blank period (when all gates output vgoff level) of 8h period will be inserted to the gates after all gates are scanned. nl1 nl0 number of lcd driver lines 0 0 0 1 1 0 24 1 1 gate driver used g1 to g24 nl2 0 0 0 0 0 0 1 0 1 1 1 0 1 56 g1 to g56 1 1 1 64 g1 to g64 0 0 0 72 g1 to g72 nl3 0 0 0 0 0 0 0 0 1 display size 396 x 24 dots 396 x 56 dots 396 x 64 dots 396 x 72 dots 0 1 0 80 g1 to g80 1 396 x 80 dots 16 g1 to g16 396 x 16 dots 48 g1 to g48 396 x 48 dots 40 g1 to g40 396 x 40 dots 32 g1 to g32 396 x 32 dots setting disabled nl4 0 0 0 0 0 0 0 0 0 0 1 0 0 88 g1 to g88 1 396 x 88 dots 0 1 1 0 96 g1 to g96 1 396 x 96 dots 0 0 0 1 104 g1 to g104 1 396 x 104 dots 0 0 1 1 112 g1 to g112 1 396 x 112 dots 0 1 0 1 120 g1 to g120 1 396 x 120 dots 0 1 1 1 128 g1 to g128 1 396 x 128 dots 0 0 0 0 136 g1 to g136 0 396 x 136 dots 1 0 1 0 144 g1 to g144 0 396 x 144 dots 1 1 0 0 152 g1 to g152 0 396 x 152 dots 1 1 1 0 160 g1 to g160 0 396 x 160 dots 1 0 0 1 168 g1 to g168 0 396 x 168 dots 1 0 1 1 176 g1 to g176 0 396 x 176 dots 1 setting disabled setting disabled
hd66770 rev.1. 1 / april 2002 20 lcd-driving-waveform control (r02h) figure 8 lcd-driving-waveform control instruction fld1-0: set number of the field that the n field inter-laced driving. for details, see the ? inter-laced ? drive section. fld1 fld0 number of field 0 0 setting disabled 0 1 1 field 1 0 setting disabled 1 1 3 field table 9 b/c: when b/c = 0, a b-pattern waveform is generated and alternates in every frame for lcd drive. when b/c = 1, a n raster-row waveform is generated and alternates in each raster-row specified by bits eor and nw5 ? nw0 in the lcd-driving-waveform control register. for details, see the n-raster-row reversed ac drive section. eor: when the c-pattern waveform is set (b/c = 1) and eor = 1, the odd/even frame-select signals and the n-raster-row reversed signals are eored for alternating drive. eor is used when the lcd is not alternated by combining the set values of the number of the lcd drive raster-row and the n raster-row. for details, see the n-raster-row reversed ac drive section. nw5 ? 0: specify the number of raster-rows n that will alternate at the c-pattern waveform setting (b/c = 1). nw5 ? nw0 alternate for every set value + 1 raster- row, and the first to the 64th raster-rows can be selected. note: fld1-0 bits are for the gate driver. control according to the bits ? value executed by the gate driver. for details, see the data sheet for the gate driver. w 1 nw1 nw0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 nw2 nw3 nw4 eor 0 b/c 0 0 0 nw5 fld1 fld0 0 0
hd66770 rev.1. 1 / april 2002 21 power control 1 (r03h) power control 2 (r0 4 h) figure 9 power control instruction sap2-0: the amount of fixed current from the operational amplifier for the source driver is adjusted. when the amount of fixed current is large, lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. during no display, when sap2-0 = ? 000 ? , the current consumption can be reduced by halting the operational amplifier and step-up circuit operation. sap2 sap1 sap0 op-amp current sap2 sap1 sap0 op-amp current 0 0 0 halt op-amp 1 0 0 medium/large 0 0 1 small 1 0 1 large 0 1 0 small/medium 1 1 0 setting disabled 0 1 1 medium 1 1 1 setting disabled table 10 table 11 bt2 ? 0: the output factor of step-up circuit is selected. adjust scale factor of the step-up circuit by the voltage used. lower amplification of the step-up circuit consumes less current. dc2-0: the operating frequency in the step-up circuit is selected. when the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. adjust the frequency considering the display quality and the current consumption. ap2 ? 0: the amount of fixed current from operational amplifier for the power supply is adjusted. when the amount of fixed current is large, the lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. during no display, when ap2-0 = ? 000 ? , the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. slp: when slp = 1, the hd66770 enters the sleep mode, where the internal display operations are halted except for the r-c oscillator, thus reducing current consumption. only serial transfer to a gate driver/power-supply ic and the following instructions can be executed during the sleep mode. power control : (bt2 ? 0, dc2 ? 0, ap 2 ? 0, slp, stb , vc2-0, cad, vr3-0, vrl3-0, vrh4-0, vcomg, vdv4-0, and vcm4-0 bits) common interface control : (te, idx) during the sleep mode, the other gram data and instructions cannot be updated although they are retained . r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 w 1 0 slp stb ap0 ap1 dc2 dc0 dc1 bt1 bt0 bt2 0 sap1 sap0 w 1 vrp3 cad ap2 0 vrp2 vrp1 vrp0 vrn3 vrn2 vrn1 vrn0 vrn4 0 vrp4 0 0 0 sap2
hd66770 rev.1. 1 / april 2002 22 stb: when stb = 1, the hd66770 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. for details, see the standby mode section. only the following instructions can be executed during the standby mode. a. standby mode cancel (stb = ? 0 ? ) b. start oscillation during the standby mode, the gram data and instructions may be lost. to prevent this, they must be set again after the standby mode is canceled. serial transfer to the common driver is possible when it is in standby mode. transfer the data again after it has been released from standby mode. cad: set up based on retention capacitor configuration of the tft panel. cad = ? 0 ? set this up when use cst compos ition. cad = ? 1 ? set this up when use cadd composition. vrp4-0: control amplitude (positive polarity) of 64-grayscale. for details, see the amplitude adjusting circuit section. vrn4-0: control amplitude (negative polarity) of 64-grayscale. for details, see the amplitude adjusting circuit section. note: bt2-0, dc2 -0, ap 2-0, slp , cad bits are for power supply ic. control according to the bits ? values is executed by power supply ic. for details, see the data sheet for the power supply ic . power control 3 (r0ch) power control 4 (r0dh) power control 5 (r0eh) figure 10 vc2-0: adjust reference voltage of vreg1out, vreg2out and vciout to optional rate of vci. also, when vc2 = ? 1 ? , it is possible to stop the internal reference voltage generator. this leads to control for vreg1out/vciout with regp and vreg2out with regn externally. vrl3-0: set magnification of amplification for vreg2out voltage (voltage for the reference voltage , vreg2 while generating vgoff.) it allows to magnify the amplification of regn from -2 to -8.5 times. pon: this is an operation starting bit for the booster circuit 3. pon = 0 is to stop and pon = 1 to start operation. vrh3- 0 : set magnification of amplification for vregout1 voltage(voltage for the reference voltage, vreg1 while generating vdh.) it allows to magnify the amplification of regp from 1.45 to 2.85 times. r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 w 1 w 1 vrh0 vrh1 vrh2 vrh3 vrl0 vrl1 vrl2 vrl3 vcm0 vcm1 vcm2 vcm3 vdv0 vdv1 vdv2 vdv3 vco mg 0 0 0 0 0 0 w 1 0 0 0 0 0 0 vc1 vc0 vc2 0 0 0 0 0 0 0 pon 0 0 0 vcm4 0 0 0 vdv4
hd66770 rev.1. 1 / april 2002 23 vcomg: when vcomg = 1, vcoml voltage can output to negative voltage (-5v). when vcomg = 0, vcoml voltage becomes gnd and stops the amplifier of the negative voltage. therefore, low power consumption is accomplished. also, when vcomg = 0 and when vcom is driven in a/c, setting of the vdv4-0 is invalid. in this case, adjustment of vcom/vgoff a/c amplitude must be adjusted with vcomh using vcm4-0. vdv4-0: sets amplification factors for vcom and vgoff while vcom ac drive is being performed. it is possible to set up from 0.6 to 1.23 times of vreg1. when vcom is not driven in a/c, the set up is invalid. vcm4-0: set vcomh voltage (voltage of higher side when vcom is driven in a/c.) it is possible to amplify from 0.4 to 0.98 times of vreg1 voltage. also, when setting up vcm4-0 = 1111, stop the internal volume adjustment and adjust vcomh with external resistance from vcomr. note: vc2 -0, vrl3 -0, vrh4 -0, vcomg, vdv4-0, vcm4-0 bits are for power supply ic. control according to the bits ? values is executed by power supply ic. for details, see the data sheet for the power supply ic . entry mode (r05h) compare register (r06h) figure 11 the write date sent from the microcomputer is modified in the hd66770 written to the gram. the display data in the gram can be quickly rewritten to reduce the load of the microcomputer software processing. for details, see the graphics operation function section. hwm: when hwm=1, data can be written to the gram at high speed. in high-speed write mode, four words of data are written to the gram in a single operation after writing to ram four times. write to ram four times, otherwise the four words cannot be written to the gram. thus, set the lower 2 bits to 0 when setting the ram address. for details, see high speed ram write mode section. i/d1-0: when i/d1-0 = 1, the address counter (ac) is automatically incremented by 1 after the data is written to the gram. when i/d1-0 = 0, the ac is automatically decremented by 1 after the data is written to the gram. the increment/decrement setting of the address counter by i/d1-0 is done independently for the upper (ad15-8) and lower (ad7-0) addresses. the direction of moving through the addresses when the gram is written to is set by the am bit. am: set the automatic update method of the ac after the data is written to the gram. when am = 0, the data is continuously written in parallel. when am = 1, the data is continuously written vertically. when window address range is specified, the gram in the window address range can be written to according to the i/d1-0 and am settings. w 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 lg0 lg1 lg2 i/d0 am hwm 0 w 1 cp1 cp0 cp2 0 0 0 0 0 0 0 i/d1 cp7 cp6 cp5 cp4 cp3 0 cp11 cp10 cp9 cp8 cp15 cp14 cp13 cp12
hd66770 rev.1. 1 / april 2002 24 figure 12 address direction settings lg2 ? 0: compare the data read from the gram by the microcomputer with the compare registers (cp11 ? 0) by a compare/logical operation and write the results to gram. for details, see the logical/compare operation function. cp15 ? 0: set the compare register for the compare operation with the data read from the gram or written by the microcomputer. figure 13 0000h af83h 0000h af83h 0000h af83h 0000h af83h 0000h af83h 0000h af83h 0000h af83h 0000h af83h i/d1-0="00" horizontal: decrement vertical: decrement i/d1-0="01" horizontal: increment vertical: decrement i/d1-0="10" horizontal: decrement vertical: increment i/d1-0="11" horizontal: increment vertical: increment am="0" horizontal am="1" vertical note: when a window address range has been set the gram can only be written to within that range. 0 0 0 1 1 db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 1 0 0 1 1 1 0 logical operation (with read data and write data) ?f ?f ?f ?f lg2-0 = "000" replace lg2-0 = "001" or lg2-0 = "010" and lg2-0 = "011" eor write data mask (wm15-0) gram write data sent from the microcomputer (db15 - 0) logical/compare operation (lg2 - 0) write data mask* (wm15 - 0) compare operation (with compare register) ?f lg2-0 = "100" replacement of matched read data ?f lg2-0 = "101" replacement of unmatched read data ?f lg2-0 = "110" replacement of matched write data ?f lg2-0 = "111" replacement of unmatched write data note: the write data mask (wm11-0) is set by the register in the ram write data mask section. 0 db12 0 db13 0 db14 0 db15
hd66770 rev.1.1 / april 2002 25 display control (r07h) figure 14 display control instruction pt1-0: normalize the source outputs when non-displayed area of the partial display is driven. for details, see the screen-division driving function section. vle2 ? 1: when vle1 = 1, a vertical scroll is performed in the 1 st screen. when vle2 = 1, a vertical scroll is performed in the 2 nd screen. vertical scrolling on the two screens can not be controlled at the same time . vle2 vle1 2 nd screen 1 st screen 0 0 fixed display fixed display 0 1 fixed display scroll display 1 0 scroll display fixed display 1 1 setting disabled table 12 cl: when cl = 1, number of colors is 8-color mode. for details, see the 8-color display mode section. cl number of display colors 0 65,536 1 8 table 13 spt: when spt = 1, the 2-division lcd drive is performed. for details, see the screen-division driving function section. w 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 vle2 0 0 0 rev vle 1 0 spt d1 d0 pt1 pt0 gon dte 0 cl
hd66770 rev.1.1 / april 2002 26 rev: displays all character and graphics display sections with reversal when rev = 1. since the grayscale level can be reversed, display of the same data is enabled on normally-white and normally- black panels figure 15 figure 16 gon: gate off level is gnd when gon = 0. dte: disptmg output is fixed to gnd when dte = 0. gon gate output dte disptmg output 0 vgon/gnd 0 halt (gnd) 1 vgon/vgoff 1 operation (vcc/gnd) table 14 table 15 i ?j combination with the partial display ii ?j combination with the d1-0 rev gram data display area non-display area pt1-0=(0 .*) pt1-0=(1.0) pt1-0=(1.1) vcom="l" vcom="h" vcom="l" vcom="h" vcom="l" vcom="h" 16'h0000 16'hffff 0 vcom="l" vcom="h" v63 v0 v0 v63 v63 v0 gnd gnd hi-z hi-z 16'h0000 16'hffff 1 v63 v0 gnd gnd hi-z hi-z v0 v63 v63 v0 source output level rev gram data d1-0=(1.0) d1-0=(0.1) d1-0=(0.0) vcom="l" vcom="h" vcom="l" vcom="h" vcom="l" vcom="h" 16'h0000 16'hffff 0 vcom="l" vcom="h" v63 v0 v0 v63 v63 v0 gnd gnd 16'h0000 16'hffff 1 v63 v0 gnd gnd d1-0=(1.1) gnd gnd gnd gnd v0 v63 v63 v0 source output level
hd66770 rev.1.1 / april 2002 27 d1 ? 0: display is on when d1 = 1 and off when d1 = 0. when off, the display data remains in the gram, and can be displayed instantly by setting d1 = 1. when d1 is 0, the display is off with all of the source outputs set to the gnd level. because of this, the hd66770 can control the charging current for the lcd with ac driving. control the display on/off while control gon and dte. for details, see the instruction set up flow. when d1 ? 0 = 01, the internal display of the hd667 70 is performed although the display is off. when d1-0 = 00, the internal display operation halts and the display is off. table 16 d bits and operation d1 d0 source output hd66770 internal display operation control signal (cl1, flm, m) 0 0 gnd halt halt 0 1 gnd operate operate 1 0 unlit display operate operate 1 1 display operate operate notes: 1. writing from the microcomputer to the gram is independent from the state of d1 ? 0. 2. in the sleep and standby modes, d1 ? 0 = 00. however, the register contents of d1 ? 0 are not modified. note: spt and gon bits are for setting the gate driver. control according to the bits ? values is executed by the gate driver. for details, see the data sheet for the gate driver . gate driver interface control (r0ah) figure 17 gate driver interface control instruction idx2-0 : index bits that select instructions for the gate driver/power supply ic. the instruction that corresponds to the setting of gate driver and power supply ic is transferred, with the index, to the gate driver and the power supply ic via the serial interface. these instructions are transferred in bit row s as shown below. the upper 3 bits correspond to idx2-0. the idx2-0 setting at the time of transfer selects the instruction for the gate driver and the power supply ic as listed below. to change an instruction setting on the gate driver and the power supply ic , first change the instruction bit on the hd667 70 at first , then, select the instruction, which includes the changed instruction bit , from the list below, by setting idx2-0 as required . the instruction is transferred to the gate driver /power supply ic after te bit is set to 1 , and is executed . te: serial transfer enable for the gate driver /power-supply ic . when 0 is read on te bit , serial transfer is possible. do not change the instruction during transfer. when 1 is written to te bit , transfer starts. te returning to 0 indicates the end of the transfer. note that, serial transfer to the gate driver /power supply ic requires 18 clock cycles at most. do not change the instruction during the transfer. * new instructions should be transfer red to the gate driver / power supply ic soon after they have been set on the hd66770. w 1 idx0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 idx1 0 0 0 0 0 0 0 0 0 idx2 te 0 r 1 idx0 idx1 0 0 0 0 0 0 0 0 0 idx2 te 0 0 0 0 0
hd66770 rev.1.1 / april 2002 28 table 17: the gate driver (hd 66770) instructions table 18: power supply ic (hd667p00) instructions figure 18 gate interface: serial transfer sequence notes: 1. transfer to the gate driver / ic chip of the power supply must take place immediately after setting up the instruction. 2. the serial transfer period takes a maximum of 1/fo s c x 18 colck cycles ( sec). 3. serial transfer cannot be executed in stand by mode. if the chip enters stand b y mode during transfer, the serial transfer is forcibly suspended. transfer must be executed again because correct transfer is not guaranteed in this situation. 4. serial transfer can be forcibly suspended by writing te = 0. transfer must be executed again because correct transfer is not guaranteed in this situation. 5. do not enter standby mode during transfer or forcibly terminate transfer except in case of emergency. before executing, confirm that the transfer is completed. instruction read te = "0" yes (transfer can be executed) no (during transfer) gate driver/ the power supply ic index ( idx2 to 0 ) te=1 ( transfer start ) index set r0ah change the instruction bit setting corresponding to the hd66770. instruction setting change including a changed instruction bit at the head based on the instruction list of hd66771/ power supply ic (hd667p00) . specify the idx2 to 0 a changed instruction bit. * transfer to the gate driver/ic chip of the power supply ic must be exercised immediately after setting up the instruction. db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 idx0 idx1 idx2 slp dc1 dc 0 ap1 0 0 0 dc2 ap0 bt2 bt1 bt0 vc0 vc1 1 0 0 vc2 0 1 0 1 1 0 cad vrh0 vrh1 vrh2 vrh3 vrl0 vrl1 vrl2 vrl3 0 vcm0 vcm1 vcm2 vcm3 vdv0 vdv1 vdv2 vdv3 vcomg 1 1 0 1 1 0 0 0 1 1 1 1 * register for hd66771 gon vrh4 ap2 0 vcm4 vdv4 0 0 setting disabled setting disabled setting disabled * * * * * * * * * * * * * * * * * * * * * * * * * * db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 idx0 idx1 idx2 0 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 slp * register for hd667p00 scn4 scn3 scn2 scn1 scn0 nl4 nl3 nl2 nl1 nl0 gs 0 fld1 fld0 0 0 0 0 0 0 0 0 gon 0 setti n g disabled 0 sett in g disabled sett in g disabled * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
hd66770 rev.1.1 / april 2002 29 frame cycle control (r0bh) figure 19 rtn3-0: set the 1h period . div1-0: set the division ratio of clocks for internal operation (div1-0). internal operation s are driven by clocks which are frequency divided according to the div1-0 setting . frame frequency can be adjusted along with the 1h period (rtn3-0). when chang i ng drive line count , adjust the frame frequency. for details, see the frame frequency adjustment function section. eq1-0: eq period can be set with eq1-0. table 19 table 20 table 21 w 1 rtn0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 rtn1 rtn2 rtn3 0 0 div0 div1 0 0 eq1 eq0 sdt1 sdt0 no0 no1 frame frequency = fosc clock cycles per raster-row x division ratio x (line + 8) [hz] fosc: cr oscillation frequency line: number of drive raster-row (nl bits) division ratio: div bit clock cycles per raster-row: rtn bits formula for the fram frequency rtn3 rtn2 0 0 rtn1 rtn0 0 0 clock cycles per raster-row 16 0 0 0 1 17 0 0 1 0 18 1 1 1 0 30 1 1 1 1 31 div1 div0 0 0 division ratio 1 0 1 2 1 0 4 1 1 8 fosc / 1 fosc / 2 fosc / 4 fosc / 8 * fosc = r-c oscillation frequency internal operation clock frequency eq1 eq0 0 0 eq period no eq 0 1 1 clock cycle 1 0 2 clock cycle 1 1 3 clock cycle
hd66770 rev.1.1 / april 2002 30 sdt1-0: set delay amount from the gate output signal falling edge of the source output s. table 22 figure 20 no1-0: set amount of non-overlap for the gate output. table 23 figure 21 sdt1 sdt0 0 0 delay amount of the source output 1 clock cycle 0 1 2 clock cycle 1 0 3 clock cycle 1 1 4 clock cycle no1 no0 0 0 amount of non-overlap 0 clock cycle 0 1 4 clock cycle 1 0 6 clock cycle 1 1 8 clock cycle 1h period 1h period non-overlap period gn gn+1 1h period 1h period delay amount of the source output gn sn equalizing period eq
hd66770 rev.1.1 / april 2002 31 gate scan position (r0fh) figure 22 table 24 figure 23: relationship between nl and scn set up value note: scn4-0 bits are for setting the gate driver. control according to the bits ? values is executed by the gate driver. for details, see the data sheet for the gate driver. r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 w 1 0 0 0 0 0 0 0 0 scn4 scn3 scn2 scn1 scn0 0 0 0 scn4-0 set the scanning starting position of the gate driver. scn4 scn3 scn2 when gs=0 scn1 scn0 when gs=1 0 0 0 g1 0 0 g228 0 0 1 g9 0 0 g220 0 0 0 g17 1 0 g212 1 0 1 0 g209 1 g20 1 1 0 1 1 g217 g12 scanning start position g1 g228 g176 g1 g228 g57 gs=0 nl=10101 scn4-0=00000 gs=0 nl=10101 scn4-0=00111 note: set nl on the gate scan end that does not exceed value of 232 or less.
hd66770 rev.1.1 / april 2002 32 vertical scroll control (r11h) figure 24 vl7-0: specify scroll length at the scroll display for vertical smooth scrolling. any raster-row from the first to 176 th can be scrolled for the number of the raster-row. after 176 th raster-row is displayed, the display restarts from the first raster-row. the display-start raster-row (vl7-0) is valid when vle1 = 1 or vle2 = 1. the raster-row display is fixed when vle2-1 = 00. table 25 1 st screen driving position (r14h) 2 nd screen driving position (r15h) figure 25 ss17 ? 0: specify the driving start position for the first screen in a line unit. the lcd driving starts from the 'set value + 1' gate driver. se17 ? 0: specify the driving end position for the first screen in a line unit. the lcd driving is performed to the 'set value + 1' gate driver. for instance, when ss17 ? 10 = 07h and se17 ? 10 = 10h are set, the lcd driving is performed from g8 to g 17, and non-selection driving is performed for g1 to g 7, g 18, and others. ensure that ss17 ? 10 se17 ? 10 afh. for details, see the screen-division driving function section. ss27 ? 0: specify the driving start position for the second screen in a line unit. the lcd driving starts from the 'set value + 1' gate driver. the second screen is driven when spt = 1. se27 ? 0: specify the driving end position for the second screen in a line unit. the lcd driving is performed to the 'set value + 1' gate driver. for instance, when spt = 1, ss27 ? 20 = 20h, and se27 ? 20 = afh are set, the lcd driving is performed from g33 to g 80. ensure that ss17 ? 10 se17 ? 10 ss27 ? 20 se27 ? 20 afh. for details, see the screen-division driving function section. w 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 vl 1 vl 0 vl 2 vl 6 vl 5 vl 4 vl 3 vl 7 0 0 0 0 0 0 0 0 note: do not set any higher raster-row than 175 ("af"h) vl1 vl0 0 0 0 1 1 0 vl2 0 0 0 1 0 1 1 1 1 vl3 0 0 0 1 1 vl4 0 0 0 0 0 vl5 0 0 0 1 1 vl6 0 0 0 0 0 scroll length 0 raster-row 1 raster-row 2 raster-row 174 raster-row 175 raster-row vl7 0 0 0 1 1 w 1 ss11 ss10 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 ss12 ss16 ss15 ss14 ss13 w 1 ss21 ss20 ss22 ss26 ss25 ss24 ss23 se11 se10 se12 se16 se15 se14 se13 se21 se20 se22 se26 se25 se24 se23 ss17 ss27 se17 se27
hd66770 rev.1.1 / april 2002 33 horizontal ram address position (r16h) vertical ram address position (r17h) figure 26 horizontal/vertical ram address position instruction hsa 7 -0/hea 7 -0: specify the horizontal start/end position s of a window for access in memory . data can be written to the gram from the address specified by hea 7 -0 from the address specified by h s a 7 -0. note that an address must be set before ram is written to . ensure 00h hsa 7 -0 hea 7 -0 3fh. vsa7-0/vea7-0: specify the vertical start/end positions of a window for access in memory . data can be written to the gram from the address specified by vea7-0 from the address specified by vsa7-0. note that an address must be set before ram is written to . ensure 00h vsa7-0 vea7-0 afh. figure 27 window address setting range note: 1. ensure that the window address area is within the gram address space. 2. in high-speed write mode, data are written to gram in four-words. thus, dummy write operations should be inserted depending on the window address area. for details, see the high-speed burst ram write function section. 3. set ram address within the window address area. in high-speed write mode, set ram address within the area containing dummy area . for details, see the high-speed ram write function section. w 1 hsa1 hsa0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 hsa2 hsa5 hsa4 hsa3 w 1 vsa1 vsa0 vsa2 vsa6 vsa5 vsa4 vsa3 hea1 hea0 hea2 hea5 hea4 hea3 vsa7 vea1 vea0 vea2 vea6 vea5 vea4 vea3 vea7 hsa7 hsa6 hea7 hea6 hsa hea "00"h ?? vsa7-0 ?? vea7-0 ?? " af"h "00"h ?? hsa7-0 ?? hea7-0 ?? "83"h vsa vea 0000h af83h gran address space window address setting range window address
hd66770 rev.1.1 / april 2002 34 ram write data mask (r20h) figure 28 ram write data mask instruction wm15 ? 0: in writing to the gram, these bits mask writing in a bit unit. when wm15 = 1, this bit masks the write data of db1 5 and does not write to the gram. similarly, the wm14 to 0 bits mask the write data of db1 4 to 0 in a bit unit. for details, see the graphics operation function section. ram address set (r21h) figure 29 ram address set instruction ad15 ? 0: initially set gram addresses to the address counter (ac). once the gram data is written, the ac is automatically updated according to the am and i/d bit settings. this allows consecutive accesses without resetting addresses. once the gram data is read, the ac is not automatically updated. gram address setting is not allowed in the standby mode. ensure that the address is set within the specified window address. table 26 gram address range in eight-grayscale mode w 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 wm 7 wm 6 wm 5 wm 4 wm 3 wm 2 wm 1 wm 0 wm 11 wm 10 wm 9 wm 8 wm 15 wm 14 wm 13 wm 12 gram setting bitmap data for g2 bitmap data for g3 bitmap data for g1 ad15 to ad0 "0000"h to "0083"h "0100"h to "0183"h "0200"h to "0283"h bitmap data for g4 "0300"h to "0383"h bitmap data for g173 "ac00"h to "ac83"h bitmap data for g174 "ad00"h to "ad83"h bitmap data for g175 "ae00"h to "ae83"h bitmap data for g176 "af00"h to "af83"h w 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 ad9 ad8 ad5 ad4 ad3 ad2 ad1 ad0 ad 10 ad 15 ad 11 ad 12 ad 13 ad 14 ad7 ad6
hd66770 rev.1.1 / april 2002 35 write data to gram (r22h) figure 30 wd15 ? 0 : write 16-bit data to the gram. this data selects the grayscale level . after a write, the address is automatically updated according to the am and i/d bit settings. during the standby mode, the gram cannot be accessed. figure 31 table 27 gram data and grayscale level gram data set-up selected grayscale 000000 00000 000001 000010 00001 000011 000100 00010 000101 000110 00011 000111 001000 00100 001001 00101 001010 001011 00110 001100 001101 00111 001110 001111 g r/b v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 n p v63 v62 v61 v60 v59 v58 v57 v56 v55 v54 v53 v52 v51 v50 v49 v48 010000 01000 010001 010010 01001 010011 010100 01010 010101 010110 01011 010111 011000 01100 011001 01101 011010 011011 01110 011100 011101 01111 011110 011111 g r/b v26 v27 v28 v29 v30 v31 n p v47 v46 v45 v44 v43 v42 v41 v40 v39 v38 v37 v36 v35 v34 v33 v32 100000 10000 100001 100010 10001 100011 100100 10010 100101 100110 10011 100111 101000 10100 101001 10101 101010 101011 10110 101100 101101 10111 101110 101111 g r/b v42 v43 v44 v45 v46 v47 n p v31 v30 v29 v28 v27 v26 v25 v24 v23 v22 v21 v20 v19 v18 v17 v16 110000 11000 110001 110010 11001 110011 110100 11010 110101 110110 11011 110111 111000 11100 111001 11101 111010 111011 11110 111100 111101 11111 111110 111111 g r/b v58 v59 v60 v61 v62 v63 n p v15 v14 v13 v12 v11 v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 v0 v16 v32 v48 v17 v33 v49 v18 v34 v50 v19 v35 v51 v20 v36 v52 v21 v37 v53 v22 v38 v54 v23 v39 v55 v24 v40 v56 v25 v41 v57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - gram data set-up selected grayscal gram data set-up selected grayscal gram data set-up selected grayscal wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 r2 r1 r0 g2 g1 g0 b1 b0 db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 gram write data b3 b2 g3 r3 wd 15 wd 14 wd 13 wd 12 r4 1 pixel b4 g5 g4 w 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 wd 15 wd 14 wd 13 wd 12
hd66770 rev.1.1 / april 2002 36 read data from gram (r22h) figure 32 read data from gram instruction rd1 5 ? 0: read 16-bit data from the gram. when the data is read to the microcomputer, the first-word read immediately after the gram address setting is latched from the gram to the internal read-data latch. the data on the data bus (db1 5 ? 0) becomes invalid and the second-word read is normal. when bit processing, such as a logical operation, is performed within the hd667 70 , only one read can be processed since the latched data in the first word is used. figure 33 gram read sequence r 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 rd 11 rd 10 rd 9 rd 8 rd 7 rd 6 rd 5 rd 4 rd 3 rd 2 rd 1 rd 0 rd 15 rd 14 rd 13 rd 12 address: n set first word second word i) data read to the microcomputer address: n set first word second word ii) logical operation processing in the hd66770 automatic address update n + a first word second word address: m set first word second word sets the i/d, am, hsa/hse, and vsa/vea bits sets the i/d, am, hsa/hse, and vsa/vea bits dummy read (invalid data) gram -> read-data latch dummy read (invalid data) gram -> read-data latch read (data of address n) read-data latch -> db15-0 write (data of address) db15-0 -> gram dummy read (invalid data) gram -> read-data latch dummy read (invalid data) gram -> read-data latch read (data of address) read-data latch -> db15-0 write (data of address n) =db15-0 -> gram
hd66770 rev.1.1 / april 2002 37 gamma control (r30h to r37h , r3f ) table 28 p k p52 ? 00: gamma micro adjustment register for the positive polarity output prp12-00: gradient adjustment register for the positive polarity output pkn52-00: gamma micro adjustment register for the negative polarity output prn12-00: gradient adjustment register for the negative polarity output vdr1-0: adjustment register for the grayscale reference value. for details, see the gamma adjustment function. w 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 0 0 0 0 w 1 0 0 0 0 w 1 0 0 0 0 w 1 0 0 0 0 r30 r31 r32 r33 w 1 0 0 0 0 w 1 0 0 0 0 w 1 0 0 0 0 w 1 0 0 0 0 r34 r35 r36 r37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pkp 00 pkp 32 pkp 31 pkp 30 pkp 22 pkp 21 pkp 20 pkp 52 pkp 51 pkp 50 pkp 42 pkp 41 pkp 40 pkn 12 pkn 11 pkn 10 pkn 02 pkn 01 pkn 00 pkn 32 pkn 31 pkn 30 pkn 22 pkn 21 pkn 20 pkn 52 pkn 51 pkn 50 pkn 42 pkn 41 pkn 40 prp 12 prp 11 prp 10 prp 02 prp 01 prp 00 prn 12 prn 11 prn 10 prn 02 prn 01 prn 00 pkp 01 pkp 02 pkp 12 pkp 11 pkp 10 w 1 0 0 0 0 r3 f 0 0 0 0 0 0 0 0 0 0 vdr 1 vdr 0
instruction list (hd66770) rev. 0.4 2001.1.19 upper code lower code reg. no. register name r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 description execution cycle ir index 0 0 * * * * * * * * * id6 id5 id4 id3 id2 id1 id0 sets the index register value. 0 sr status read 1 0 l7 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 reads the driving raster-row position (l7-0). 0 start oscillation 0 1 * * * * * * * * * * * * * * * 1 starts the oscillation mode. 10 ms r00h device code read 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 reads 0770h. 0 r01h driver output control 0 1 0 0 0 0 0 0 gs ss 0 0 0 nl4 nl3 nl2 nl1 nl0 sets the gate driver shift direction (gs), source driver shift direction (ss), and number of driving lines (nl4-0). 0 r02h lcd-driving- waveform control 0 1 0 0 0 0 fld1 fld0 b/c eor 0 0 nw5 nw4 nw3 nw2 nw1 nw0 sets the lcd drive ac waveform (b/c), number of interlaced field (fld1- 0), eor output (eor), and the number of n-raster-rows (nw5-0) at c- pattern ac drive. 0 r03h power control 1 0 1 0 0 sap2 sap1 sap0 bt2 bt1 bt0 dc2 dc1 dc0 ap2 ap1 ap0 slp stb sets the standby mode (stb), lcd power on (ap1-0), sleep mode (slp), boosting cycle (dc2-0), boosting output multiplying factor (bt3-0), and source op-amp on (sap2-0). 0 r04h power control 2 0 1 cad 0 0 vrn4 vrn3 vrn2 vrn1 vrn0 0 0 0 vrp4 vrp3 vrp2 vrp1 vrp0 sets the grayscale adjusting generator (vrn4-0, vrp4-0) and configuration of retention volume (cad). 0 r05h entry mode 0 1 0 0 0 0 0 0 hwm 0 0 0 i/d1 i/d0 am lg2 lg1 lg0 specifies the logical operation (lg2-0), ac counter mode (am), increment/decrement mode (i/d1-0) and high-speed-write mode (hwm). 0 r06h compare register 0 1 cp15 cp14 cp13 cp12 cp11 cp10 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0 sets the compare register (cp15-0). 0 r07h display control 0 1 0 0 0 pt1 pt0 vle2 vle1 spt 0 0 gon dte cl rev d1 d0 specifies display on (d1-0), reversed display (rev), number of display colors (cl), disptmg enable (dte), gate output on (gon), screen division driving (spt), and vertical scroll (vle2-1) and source output condition (pt1-0). 0 0 1 0 0 0 0 0 0 0 te 0 0 0 0 0 idx2 idx1 idx0 0 r0ah com driver interface control 1 1 0 0 0 0 0 0 0 te 0 0 0 0 0 idx2 idx1 idx0 specifies the serial transfer enable (te) and index for the power supply transfer instructions (idx2-0). 0 r0bh frame cycle control 0 1 no1 no0 std1 std0 eq1 eq0 div1 div0 0 0 0 0 rtn3 rtn2 rtn1 rtn0 sets the 1h period (rtn3-0) and operating clock frequency-division ratio (div1-0), the equalizing period (eq1-0), delay volume of the source output (std1-0), non-overlap volume of the gate output (no1-0). 0 r0ch power control 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 vc2 vc1 vc0 sets an adjustment factor for the vci voltage (vc2-0). 0 r0dh power control 4 0 1 0 0 0 0 vrl3 vrl2 vrl1 vrl0 0 0 0 pon vrh3 vrh2 vrh1 vrh0 sets the amplification factor for vregout1 voltage (vrh4-0) and for vregout2 voltage (vrl3-0). 0 r0eh power control 5 0 1 0 0 vcom g vdv4 vdv3 vdv2 vdv1 vdv0 0 0 0 vcm4 vcm3 vcm2 vcm1 vcm0 sets vcomh voltage (vcm4-0), ac-cycle oscillation of vcom and vgoff (vdv3-0) and voltage of vcom (vcomg) 0 r0fh gate scanning starting position 0 1 0 0 0 0 0 0 0 0 0 0 0 scn4 scn3 scn2 scn1 scn0 sets the scanning starting position (scn4-0) of the gate driver. 0 r11h vertical scroll control 0 1 0 0 0 0 0 0 0 0 vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 specifies the screen display scroll volume (vl7-0). 0 r14h 1st screen driving position 0 1 se17 se16 se15 se14 se13 se12 se11 se10 ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 sets 1st-screen driving start (ss17-10) and end (se17-10). 0 r15h 2nd screen driving position 0 1 se27 se26 se25 se24 se23 se22 se21 se20 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 sets 2nd-screen driving start (ss27-20) and end (se27-20). 0 r16h horizontal ram address position 0 1 hea7 hea6 hea5 hea4 hea3 hea2 hea1 hea0 hsa7 hsa6 hsa5 hsa4 hsa3 hsa2 hsa1 hsa0 sets the start (hsa7-0) and end (hea7-0) of the horizontal ram address range. 0 r17h vertical ram address position 0 1 vea7 vea6 vea5 vea4 vea3 vea2 vea1 vea0 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 sets the start (vsa7-0) and end (vea7-0) of the vertical ram address range. 0 r20h ram write data mask 0 1 wm15 wm14 wm13 wm12 wm11 wm10 wm9 wm8 wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 specifies write data mask (wm15-0) at ram write. 0 r21h ram address set 0 1 ad15-8 (upper) ad7-0 (lower) initially sets the ram address to the address counter (ac). 0 write data to ram 0 1 write data (upper) write data (lower) write data to ram. 0 r22h write data from ram 1 1 read data (upper) read data (lower) read data from ram. 0 38 hd66770 rev.1.1
r30h gamma control (1) 0 1 0 0 0 0 0 pkp12 pkp11 pkp10 0 0 0 0 0 pkp02 pkp01 pkp00 adjust the gamma control. 0 r31h gamma control (2) 0 1 0 0 0 0 0 pkp32 pkp31 pkp30 0 0 0 0 0 pkp22 pkp21 pkp20 adjust the gamma control. 0 r32h gamma control (3) 0 1 0 0 0 0 0 pkp52 pkp51 pkp50 0 0 0 0 0 pkp42 pkp41 pkp40 adjust the gamma control. 0 r33h gamma control (4) 0 1 0 0 0 0 0 prp12 prp11 prp10 0 0 0 0 0 prp02 prp01 prp00 adjust the gamma control. 0 r34h gamma control (5) 0 1 0 0 0 0 0 pkn12 pkn11 pkn10 0 0 0 0 0 pkn02 pkn01 pkn00 adjust the gamma control. 0 r35h gamma control (6) 0 1 0 0 0 0 0 pkn32 pkn31 pkn30 0 0 0 0 0 pkn22 pkn21 pkn20 adjust the gamma control. 0 r36h gamma control (7) 0 1 0 0 0 0 0 pkn52 pkn51 pkn50 0 0 0 0 0 pkn42 pkn41 pkn40 adjust the gamma control. 0 r37h gamma control (8) 0 1 0 0 0 0 0 prn12 prn11 prn10 0 0 0 0 0 prn02 prn01 prn00 adjust the gamma control. 0 r3fh gamma control (9) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vdr1 vdr0 adjust the gamma control. 0 note: 1. * means 'doesn't matter'. 2. after setting te = 1, 18 (max.) clock cycles are required for a serial transfer to be completed. during that time, do not change the bits of instructions, which are to be transferred. 3. high-speed write mode is available only for the ram writing. 39 hd66770 rev. 1.1
hd66770 rev.1.1 /april 2002 40 reset function the hd66770 is internally initialized by reset input. reset the gate driver /power supply ic as its setting s are not automatically reinitialized when the hd66770 is reset . the reset input must be held for at least 1 ms. do not access the gram or initially set the instructions until the r-c oscillation frequency is stable after power has been supplied (10 ms). instruction set initialization: 1. start oscillation executed 2. driver output control (nl4 ? 0 = 10101, ss = 0, cs = 0) 3. lcd driving ac control ( fld1-0 = 01, b/c = 0, e o r = 0, nw5 ? 0 = 00000 ) 4. power control 1 ( sap2-0 = 000, bt2-0 = 000, dc2 ? 0 = 000, ap 2 ? 0 = 0 00: lcd power off, slp = 0, stb = 0: standby mode off) 5. power control 2 (cad = 0, vrn4-0 = 0000, vrp4-0 = 0000 6. entry mode set (hwm = 0, i/d1-0 = 11: increment by 1, am = 0: horizontal move, lg2 ? 0 = 000: replace mode) 7. compare register (cp 15 ? 0: 00000000 00000000 ) 8. display control ( pt1-0 = 00, vle2 ? 1 = 00: no vertical scroll, spt = 0, gon = 0, dte = 0, cl = 0: 65536 color mode, rev = 0, d1 ? 0 = 00: display off) 9. com driver interface control (te = 0, idx2-0 = 000) 10. frame cycle control ( no1-0 = 00, sdt1-0 = 00, eq1-0 = 00: no equalizer, div1-0 = 00: 1-divided clock, rtn3-0 = 0000 : 16 clock cycle in 1h period) 11. power control 3 (vc2-0 = 000) 12. power control 4 (vrl3-0 = 0000, pon=0 vrh3-0= 00000 ) 13. power control 5 (vcomg = 0, vdv4-0 = 00000, vcm4-0 = 00000 14. gate scanning starting position (scn4-0 = 00000) 15 . vertical scroll (vl7 ? 0 = 0000000) 1 6 . 1st screen division (se17-10 = 11111 111, ss17-10 = 00000000) 17. 2nd screen division (se27-20 = 11111111, ss27-20 = 00000000) 18. horizontal ram address position (hea 7 -0 = 1000 00 11, hsa 7 -0 = 000000 00 ) 19. vertical ram address position (vea7-0 = 10101111, vsa7-0 = 00000000) 20. ram write data mask (wm1 5 ? 0 = 0 000h: no mask) 21. ram address set (ad1 5 ? 0 = 0000h) 22. gamma control ( p k p 0 2 ? 00 = 0 0 0, p k p 1 2 ? 10 = 00 0 , p k p 2 2 ? 20 = 0 00, p k p 32 ? 30 = 0 00 , p k 4 2 ? 4 0 = 00 0 , p k p 5 2 ? 5 0 = 00 0, p r p02 ? 0 0 = 000 , p rp12 ? 1 0 = 00 0 ) ( p k n 02 ? 0 0 = 00 0 , p k n12 ? 10 = 0 0 0, p k n22 ? 20 = 0 0 0 , p k n32 ? 30 = 0 0 0 , p k n42 ? 40 = 0 0 0, p k n52 ? 50 = 0 0 0, p rn02 ? 00 = 00 0 , p rn12 ? 10 = 0 00) (vdr ? 1 = ? 00 ? ) gram data initialization: this is not automatically initialized by reset input but must be initialized by software while display is off (d1 ? 0 = 00).
hd66770 rev.1.1 /april 2002 41 output pin initialization: 1. lcd driver output pins ( source output ): output gnd level 2. oscillator output pin (osc2): outputs oscillation sign al 3. gate interface signals (gcs*, gcl, and gda): halt 4. timing signals (cl1, m, flm, disptmg, and dcclk): halt parallel data transfer 16-bit bus interface setting the im2/ 1/ 0 (interface mode) to the gnd/gnd/gnd level allows 68-system e-clock- synchronized 16-bit parallel data transfer. setting the im2 /1 /0 to the gnd/vcc/gnd level allows 80-system 16-bit parallel data transfer. when the number of buses or the mounting area is limited, use an 8-bit bus interface. figure 34 interface to 16-bit microcomputer 8-bit bus interface setting the im2/ 1/ 0 (interface mode) to the gnd/gnd/vcc level allows 68-system e-clock- synchronized 8-bit parallel data transfer using pins db15 ? db8. setting the im1/0 to the vcc/vcc level allows 80-system 8-bit parallel data transfer. the 16-bit instructions and ram data are divided into eight upper/lower bits and the transfer starts from the upper eight bits. fix unused pins db7 ? db0 to the vcc or gnd level. note that the upper bytes must also be written when the index register is written to. figure 35 interface to 8-bit microcomputer csn* a1 hwr* (rd*) d15 - d0 cs* rs wr* (rd*) db15 - db0 h8/2245 hd667 70 16 csn* a1 hwr* (rd*) d15 - d8 cs* rs wr* (rd*) db15 - db8 db7 - 0 h8/2245 hd66770 8 8
hd66770 rev.1.1 /april 2002 42 note: transfer synchronization function for an 8-bit bus interface the hd66770 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00h instruction four times. the next transfer starts from the upper eight bits. executing synchronization function periodically can recover any runaway in the display system. figure 36 8-bit transfer synchronization "00"h "00"h "00"h "00"h rs r/w e db15 to db8 upper lower 8-bit transfer synchronization (1) (2) (3) (4) upper or lowe
hd66770 rev.1.1 / april 2002 43 serial data transfer setting the im1 pin to the gnd level and the im2 pin to the vcc level allows standard clock-synchronized serial data (spi) transfer, using the chip select line (cs*), serial transfer clock line (scl), serial input data (sdi), and serial output data (sdo). for a serial interface, the im0/id pin function uses an id pin. if the chip is set up for serial interface, the db15-2 pins which are not used must be fixed at vcc or gnd. the hd667 70 initiates serial data transfer by transferring the start byte at the falling edge of cs* input. it ends serial data transfer at the rising edge of cs* input. the hd66770 is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the hd66770. the hd667 70 , when selected, receives the subsequent data string. the least significant bit of the identification code can be determined by the id pin. the five upper bits must be 01110. two different chip addresses must be assigned to a single hd66770 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, data can be written to the index register or status can be read, and when rs = 1, an instruction can be issued or data can be written to or read from ram. read or write is selected according to the eighth bit of the start byte (r/w bit). the data is received when the r/w bit is 0, and is transmitted when the r/w bit is 1. after receiving the start byte, the hd667 70 receives or transmits the subsequent data byte- by-byte. the data is transferred with the msb first. all hd667 70 instructions are 16 bits. two bytes are received with the msb first (db15 to 0), then the instructions are internally executed. after the start byte has been received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is fetched internally as the lower eight bits of the instruction. four bytes of ram read data after the start byte are invalid. the hd667 70 starts to read correct ram data from the fifth byte. table 30 start byte format transfer bit s 1 2 3 4 5 6 7 8 start byte format transfer start device id code rs r/w 0 1 1 1 0 id note: id bit is selected by the im0/id pin. table 31 rs and r/w bit fu nction rs r/w function 0 0 sets index register 0 1 reads status 1 0 writes instruction or ram data 1 1 reads instruction or ram data
hd66770 rev.1.1 / april 2002 44 start byte instruction 1: execution time scl (input) b) timing of consecutive data-transfer through clock-synchronized serial bus interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 instruction 1: upper eight bits instruction 2: lower eight bits 20 21 22 23 24 25 26 27 28 29 30 31 32 instruction 2: upper eight bits start end cs* (input) sdi (input) note: the first byte after the start byte is always the upper eight bits. start byte rs=1, r/w=1 c) ram-data read-transfer timing start end dummy read 1 dummy read 2 dummy read 3 dummy read 4 dummy read 5 ram read: upper eight bits ram read: lower eight bits note: five b y tes of the ram read data after the start byte are invalid. the hd66770 starts to read the correct ram data from the sixth byte. a) timing basic data transfer through clock synchronized serial bus interface start byte index register setting, instruction, ram data wite scl (input) transfer start transfer end sdi (input) devise id code msb "0" lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 "1" "1" "1" "0" id rs rw db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 rs rw sdo (output) status read, instruction read, ram data read db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0
hd66770 rev.1.1 / april 2002 45 figure 38: procedure for transfer on clock-synchronized serial bus interface ( 2 ) start byte rs = 1, r/w = 1 scl (input) d) status read / instruction read start end cs* (input) sdi (input) sdo (output) dummy read 1 status read: upper 8 bits status read: lower 8 bits note: one byte of the read data after the start byte are invalid. the hd66770 starts to read the correct data from the second byte.
hd66770 rev.1.1 / april 2002 46 high-speed burst ram write function the hd66770 has a high-speed burst ram-write function that can be used to write data to ram in one- fourth the access time required for an equivalent standard ram-write operation. this function is especially suitable for applications which require the high-speed rewriting of the display data, for example, display of color animations, etc. when the high-speed ram-write mode (hwm) is selected, data for writing to ram is once stored to the hd667 70 internal register. when data is selected four times per word, all data is written to the on-chip ram. while this is taking place, the next data can be written to an internal register so that high-speed and consecutive ram writing can be executed for animated displays, etc. index ?i r22 ?j e (input) b) example of the operation of high-speed consecutive writing to ram (16-bit bus interface) cs* (input) db15-0 (input/output) ram data 1 ram data 1 to 4 ram write data (64 bits) ram write execution time ram data 5 to 8 ram data 2 ram data 3 ram data 4 ram data 5 ram data 6 ram data 7 ram data 8 ram wite execution time ram address (ac15-0) "0000"h ram data 9 to 12 ram write execution time* ram data 9 ram data 10 ram data 11 ram data 12 index 1 2 3 4 1 2 3 4 1 2 3 4 "0004"h "0008"h "000a"h * the lower two bits of the address must be set in the following way in high-speed write mode. when id0 becomes 0, the lower two bits of the address must be set to 11 when id1 becomes 1, the lower two bits of the address must be set to 00. note: when a high-speed ram write is canceled, the next instruction must only be executed after the ram write execution time has elapsed. figure 42 flow of operation in high-speed consecutive writing to ram register 1 register 2 register 3 register 4 gram 16 64 address counter ?i ac ?j 16 microcomputer "0000"h "0001"h "0002"h "0003"h a) the action flow of the high-speed burst ram write register 1 register 2 register 3 register 4 gram address counter (ac) microcomputer "0000"h "0001"h "0002"h "0003"h a) the action flow of the high-speed burst ram write
d66770 rev.1.1 / april 2002 47 by using high-speed burst ram write function , data is written to ram each four words. therefore when using 8-bit bus interface, data will be stored 8 times to internal register before written to ram c) example of the operation of high-speed consecutive writing to ram ( 8-bit bus interface ) * the lower two bits of the address must be set in the following way in high-speed write mode. when id0 becomes 0, the lower two bits of the address must be set to 11. when id1 becomes 0, the lower two bits of the address must be set to 00. index ?i r22 ?j e ( input) cs * ( input) db15-0 ram write data ( 64-bit ) ram data (5) - (8) ram write execution time ram address ( ac15-0 ) "0000"h 1 2 3 4 5 6 7 8 1 2 3 4 "0004"h 5 6 7 8 ram write execution time ?? ( input/ output) ram data ( 1 ) - ( 4 ) ram data (1) ram data (1) ram data (2) ram data ( 2 ) ram data (3) ram data ( 3 ) ram data (4) ram data ( 4 ) ram data (1) ram data (1) ram data (2) ram data ( 2 ) ram data (3) ram data ( 3 ) ram data (4) ram data ( 4 )
d66770 rev.1.1 / april 2002 48 when high-speed ram write mode is used, note the following. notes: 1. the logical and compare operations cannot be used. 2. data is written to ram each four words. when an address is set, the lower two bits in the address must be set to the following values. *when id0=0, the lower two bits in the address must be set to 11 and be written to ram. *when id0=1, the lower two bits in the address must be set to 00 and be written to ram. 3. data is written to ram each four words. if less than four words of data is written to ram, the last data will not be written to ram. 4. when the index register and ram data write (r22h) have been selected, the data is always written first. ram cannot be written to and read from at the same time. hwm must be set to 0 while ram is being read. 5. high-speed and normal ram write operations cannot be executed at the same time. the mode must be switched and the address must then be set. 6. when high-speed ram write is used with a window address-range specified, dummy writ e operation may be required to suit the window address range-specification. refer to the high- speed ram write in the window address section. table 32 comparison between normal and high-speed ram write operations normal ram write (hwm=0) high-speed ram write (hwm=1) logical operation function can be used cannot be used compare operation function can be used cannot be used write mask function can be used can be used ram address set can be specified by word id0 bit=0: set the lower two bits to 11 id0 bit=1: set the lower two bits to 00 ram read can be read by word cannot be used ram write can be written by word dummy write operations may have to be inserted according to a window address-range specification window address can be set by word set necessary more than four word
hd66770 rev.1.1 / april 2002 49 high-speed ram write in the window address when a window address range is specified, ram data which is in an optional window area can be rewritten consecutively and quickly by inserting dummy write operations so that ram access counts become 4n as shown in the tables below. dummy write operations may have to be inserted as the first or last operations for a row of data, depending on the horizontal window-address range specification bits (hsa1 to 0, hea1 to 0). number of dummy write operations of a row must be 4n. table 3 3 number of dummy write operations in high-speed ram write (hsa bits) hsa1 hsa0 number of dummy write operations to be inserted at the start of a row 0 0 0 0 1 1 1 0 2 1 1 3 table 3 4 number of dummy write operations in high-speed ram w rite (hea bits) hea1 hea0 number of dummy write operations to be inserted at the end of a row 0 0 3 0 1 2 1 0 1 1 1 0 each row of access must consist of 4 n operations, including the dummy writes. horizontal access count = first dummy write count + write data count + last dummy write count = 4 n
hd66770 rev.1.1 / april 2002 50 an example of high-speed ram write with a window address-range specified is shown below. the window address-range can be rewritten to consecutively and quickly by inserting two dummy writes at the start of a row and three dummy writes at the end of a row, as determined by using the window address-range specification bits (hsa1 to 0 = 10, hea1 to 0 = 00). h0000 haf83 gram address map ha030 window address-range setting hsa=h12, hea=h30 vsa=h80, vea=ha0 high-speed ram write mode setting hwm = 1 address set ad = h0810 *1 dummy ram write x 2 ram write x 31 dummy ram write x 3 x 152 note: the address set for the high-speed ram write must be 00 or 11 according to the value of the id0 bit. only ram in the specified window address-range will be over written. h0812 window address- range specification ( rewrite area) window address-range setting hsa=h12, hea=h30 vsa=h80, vea=ha0 writing in the horizontal direction am = 0, id0 = 1 figure 45: example of the high-speed ram write with a window address-range specification
hd66770 rev.1.1 / april 2002 51 window address function when data is written to the on-chip gram, a window address-range which is specified by the horizontal address register (start: hsa 7 -0, end: hea 7 -0) or the vertical address register (start: vsa7-0, end: vea7- 0) can be written to consecutively. data is written to addresses in the direction specified by the am bit (increment/decrement). when image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. the window must be specified to be within the gram address area described below. addresses must be set within the window address. [restriction on window address-range settings] ( horizontal direction) 00h hsa 7 -0 hea 7 -0 8 3h ( vertical direction) 00h vsa7-0 vea7-0 afh [restriction on address settings during the window address] (ram address) hsa7 to 0 ad 7 -0 hea 7 -0 vsa7-0 ad15-8 vea7-0 note: in high-speed ram-write mode, the lower two bits of the address must be set as shown below according to the value of the id0 bit. id0 = 0: the lower two bits of the address must be set to 11. id0 = 1: the lower two bits of the address must be set to 00.
hd66770 rev.1.1 / april 2002 52 figure 4 6 example of address operation in the window address specification window address-range specification area hsa7-0 = "10"h ?a hse7-0 = "2f"h vsa7-0 = "20"h ?a vea7-0 = "5f"h i/d = 1 (increment) am = 0 (horizontal writing) "af00"h "af83"h "0000"h "0083"h "2010"h "202f"h "5f10"h "5f2f"h "2110"h "212f"h gram address map window address area
hd66770 rev.1.1 / april 2002 53 graphics operation function the hd66770 can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. this function supports the following: 1. a write data mask function that selectively rewrites some of the bits in the 1 6 -bit write data. 2. a logical operation write function that writes the data sent from the microcomputer and the original ram data by a logical operation. 3. a conditional write function that compares the original ram data or write data and the compare- bit data and writes the data sent from the microcomputer only when the conditions match. even if the display size is large, the display data in the graphics ram (gram) can be quickly rewritten. the graphics bit operation can be controlled by combining the entry mode register, the bit set value of the ram-write-data mask register, and the read/write from the microcomputer. table 3 5 graphics operation bit setting operation mode i/d am lg2 ? 0 operation and usage write mode 1 0/1 0 000 horizontal data replacement, horizontal-border drawing write mode 2 0/1 1 000 vertical data replacement, vertical-border drawing write mode 3 0/1 0 110 111 conditional horizontal data replacement, horizontal-border drawing write mode 4 0/1 1 110 111 conditional vertical data replacement, vertical-border drawing read/write mode 1 0/1 0 001 010 011 horizontal data write with logical operation, horizontal- border drawing read/write mode 2 0/1 1 001 010 011 vertical data write with logical operation, vertical-border drawing read/write mode 3 0/1 0 100 101 conditional horizontal data replacement, horizontal-border drawing read/write mode 4 0/1 1 100 101 conditional vertical data replacement, vertical-border drawing
hd66770 rev.1.1 / april 2002 54 w rite-data mask function the hd6677- has a bit-wise write-data mask function that controls writing the two-byte data from the microcomputer to the gram. bits that are 0 in the write-data mask register (wm1 5 ? 0) cause the corresponding db bit to be written to the gram. bits that are 1 prevent writing to the corresponding gram bit to the gram; the data in the gram is retained. this function can be used when only one- pixel data is rewritten or the particular display color is selectively rewritten. figure 48 example of write-data mask function operation logical/compare operation (lg2-0:) write bit mask write-data latch graphics ram ( gram) 000: replacement, 001:or, 010: and, 011:eor, 100: replacement with matched read, 101: replacement with unmatched read, 110: replacement with matched write, 111: replacement with unmatched write microcompute address counter (ac) logical operation bit (lg2-0) 3 16 16 write-mask register (wm15-0) 16 16 +1/-1 + 256 16 16 16 figure 4 7 data processing flow of the graphic operation compare bit (cp15-0) 16 read-data latch db15 db0 write-data mask wm15 wm0 1 1 1 1 0 0 0 1 db15 db0 gram data r 02 r 01 r 00 r 03 g 02 g 01 g 00 g 03 g 02 g 01 g 03 1 1 0 0 b 02 b 01 b 00 b 03 1 b 04 0 g 04 0 g 05 1 r 04 b 01 b 00 * g 05 g 04 data written by the microcomputer * * * * * * * *
hd66770 rev.1. 1 / april 2002 55 graphics operation processing 1. write mode 1: am = 0, lg2 ? 0 = 000 this mode is used when the data is horizontally written at high speed. it can also be used to initialize the graphics ram (gram) or to draw borders. the write-data mask function (wm1 5 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the gram. figure 4 9 writing operation of write mode 1 wm15 wm0 operation examples: 1) i/d = "1", am = "0", lg2-0 = "000" 2) wm15-0 = "07ff"h 3) ac = "0000"h write-data mask: 0 1 1 1 1 1 1 1 1 db15 db0 write data (1): 1 0 0 1 1 0 0 1 0 1 0 0 write data (2): 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 * * * * * * * * 1 1 0 * * * * * * * * "0000"h "0001"h "0002"h write data (1) write data (2) gram note: the bits in the gram indicated by '*' are not changed 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 * * 0 * * 1 1 1 * * *write mask for plain and
hd66770 rev.1. 1 / april 2002 56 2. write mode 2: am = 1, lg2 ? 0 = 000 this mode is used when the data is vertically written at high speed. it can also be used to initialize the gram, develop the font pattern in the vertical direction, or draw borders. the write-data mask function (wm1 5 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper- left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. operation examples: 1) i/d = "1", am = "1" , lg2-0 = "000" 2) wm15-0 = "07ff"h 3) ac = "0000"h note: 1. the bits in the gram indicated by '*' are not changed. 2. after writing to address "af00"h, the ac jumps to "000"h. wm15 wm0 write-data mask: 0 0 0 0 1 1 1 1 1 1 1 1 db15 db0 write data (1): 1 0 0 1 1 0 0 1 0 1 0 0 write data (2): 1 1 0 0 0 0 1 1 0 0 0 0 write data (3): 0 1 1 1 0 1 0 0 0 0 0 1 "0000"h write data (1) gram "0100"h "0200"h write data (2) write data (3) 1 0 0 1 1 1 0 0 0 1 1 1 * * * * * * * * * * * * * * * * * * * * * * * * 0 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 0 1 * * * * * * * * * figure 50 writing operation of write mode 2
hd66770 rev.1. 1 / april 2002 57 3. write mode 3: am = 0, lg2 ? 0 = 110/111 this mode is used when the data is horizontally written by comparing the write data and the set value of the compare register (cp15 ? 0). when the result of the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the gram. in this operation, the write-data mask function (wm15 ? 0) is also enabled. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the gram. operation examples: 1) i / d = "1", am = "0" , lg2-0 = "110" (matched wite) 2) cp15-0 = "2860"h 2) wm15-0 = "0000"h 3) ac = "0000"h wm15 wm0 write-data mask: 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 "0000"h "0001"h gram write data (1): write data (2): 0 0 0 0 1 1 1 1 0 0 0 0 compare operation cp15 cp0 compare register 0 1 0 1 0 0 1 1 replacement conditional replacement c c r r * (matched) * * * * * * * * * * * conditional replacement * * * * * * * * * * * * 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 * * * * 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 * * * * compare operation matched replacement of write data (1) figure 51 writing operation of write
hd66770 rev.1. 1 / april 2002 58 4. write mode 4: am = 1, lg2 ? 0 = 110/111 this mode is used when a vertical comparison is performed between the write data and the set value of the compare register (cp15 ? 0) to write the data. when the result by the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the gram. in this operation, the write-data mask function (wm15 ? 0) are also enabled. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. operation examples: 1) i/d = "1", am = "1", lg2-0 = "111" (unmatched write) 2) cp15-0 = "2860"h 2) wm15-0 = "0000"h 3) ac = "0000"h wm15 wm0 write-data mask: 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 write data (1): 1 0 0 1 1 0 0 1 write data (2): compare operation compare operation cp15 cp0 compare register: 0 0 1 0 1 0 0 0 conditional replacement conditional replacement c c r r (unmatched) (matched) 1 0 0 1 1 0 0 1 * * * * * * * * * * * * "0000"h write data (1) gram "0100"h write data (2) "af00"h "0000"h "0001"h 1 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 * * * * * * * * * * * * 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 * 1 * 1 * 1 * * * * * note: 1. the bits in the gram indicated by '*' are not changed. 2. after writing to address "af00"h, the ac jumps to "0001"h. figure 52 writing operation of write mode 4
hd66770 rev.1. 1 / april 2002 59 5. read/write mode 1: am = 0, lg2 ? 0 = 001/010/011 this mode is used when the data is horizontally written at high speed by performing a logical operation with the original data. it reads the display data (original data), which has already been written in the gram, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the gram. this mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as the write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read- data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm1 5 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edges of the gram. wm15 wm0 operation examples: 1) i/d = "1", am = "0" , lg2-0 = "001"(or) 2) wm15-0 = "0000"h 3) ac = "0000"h write-data mask: 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 write data (1): 1 0 1 1 1 1 0 0 0 1 1 0 write data (2): 1 1 0 0 0 0 1 1 1 0 0 0 "0000"h "0001"h read data + write data (1) gram read data (1): 1 0 0 1 1 0 0 1 0 1 0 0 read data (2): 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 1 1 0 0 0 logical operation(or) logical operation(or) 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 0 1 1 0 read data (2) + write data (2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5 3 writing operation of read/write mode 1
hd66770 rev.1. 1 / april 2002 60 6. read/write mode 2: am = 1, lg1 ? 0 = 001/010/011 this mode is used when the data is vertically written at high speed by performing a logical operation with the original data. it reads the display data (original data), which has already been written in the gram, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the gram. this mode can read the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write- data mask function (wm15 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. wm15 wm0 operation examples: 1) i / d = "1", am = "1" , lg2-0 = "001"(or) 2) wm15-0 = "ffe0"h 3) ac = "0000"h write-data mask: 1 1 1 1 1 1 1 1 1 1 1 0 db15 db0 write data (1): 1 0 1 1 1 1 0 0 0 1 1 0 write data (2): 1 1 0 0 0 0 1 1 1 0 0 0 read data (1): 1 0 0 0 1 0 0 1 0 1 0 1 read data (2): 0 0 0 0 1 1 1 1 0 0 0 0 logical operation(or) "0000"h read data (1) + write data (1) gram "0100"h read data (2) + write data (2) note: 1. the bits in the gram indicated by '*' are not changed. 2. after writing to address "af00"h, the ac jumps to "0001"h. 1 1 1 0 1 0 1 1 1 1 0 1 0 "af00"h "0000"h "0001"h logi c al operation(or) 1 * * * * * * * * * * * * * * * * 1 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 * * * * * * figure 5 4 writing operation of read/write mode 2
hd66770 rev.1. 1 / april 2002 61 7. read/write mode 3: am = 0, lg2 ? 0 = 100/101 this mode is used when the data is horizontally written by comparing the original data and the set value of compare register (cp15 ? 0). it reads the display data (original data), which has already been written in the gram, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the gram only when the result of the comparison satisfies the condition. this mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read- data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm1 5 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edges of the gram. operation examples: 1) i/d = "1", am = "0" , lg2-0 = "100" (matched write) 2) cp15-0 = "2860"h 2) wm15-0 = "0000"h 3) ac = "0000"h wm15 wm0 write-data mask: 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 write data (1): 1 0 1 1 1 1 0 0 0 1 1 0 write data (2): 1 1 0 0 0 0 1 1 1 0 0 0 "0000"h "0001"h gram read data (1): read data (2): 0 0 0 0 1 1 1 1 0 0 0 0 compare operation compare operation cp15 cp0 compare register: 0 0 1 0 1 0 0 0 conditional replacement conditional replacement c c r r 0 0 0 0 1 1 1 1 0 0 0 0 matched 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 matched replacement write data (1) figure 5 5 writing operation of read/write mode 3
hd66770 rev.1. 1 / april 2002 62 8 . read/write mode 4: am = 1, lg2 ? 0 = 100/101 this mode is used when the data is vertically written by comparing the original data and the set value of the compare register (cp15 ? 0). it reads the display data (original data), which has already been written in the gram, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the gram only when the result of the compare operation satisfies the condition. this mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as the write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write- data mask function (wm15 ? 0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. f igure 5 6 writing operation of read/write mode 4 operation examples: 1) i / d = "1", am = "1", lg2-0 = "101" (unmatched write) 2) cp15-0 = "2860"h 2) wm15-0 = "0000"h 3) ac = "0000"h wm1 5 wm 0 write-data mask: 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 write data (1): 1 0 1 1 1 1 0 0 0 1 1 0 write data (2): 1 1 0 0 0 0 1 1 1 0 0 0 read data (1): 1 0 0 1 1 0 0 1 0 1 0 1 read data (2): compare operation compare operation cp15 cp0 compare register: 0 0 1 0 1 0 0 0 conditional replacement condit i onal replacement c c r r unmatched "0000"h write data (1) gra "0100"h write data (2) note: 1. the bits in the gram indicated by '*' are not changed. 2. after writing to address "af00"h, the ac jumps to "0001"h. "af00"h "0000"h "0001"h 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 m atched
hd66770 rev.1. 1 / april 2002 63 gamma adjustment function the hd66770incorporates gamma adjustment function for the 65 ,536-color display . gamma adjustment is implemented by deciding the 8-grayscale level with angle adjustment and micro adjustment register. also, angle adjustment and micro adjustment is fixed for each of the internal positive and negative polarity. set up by the liquid crystal panel ? s specification. r 3 r 2 r 1 g 2 g 1 g 0 b 3 b 2 display data msb lsb graphics ram (gram) r 0 g 3 b 1 b 0 b 4 g 4 g 5 r 4 32 grayscale control 64 grayscale control 32 grayscale control 5 6 5 lcd driver lcd driver lcd drver r g b lcd pkp 01 pkp 00 pkp 11 pkp 10 pkp 21 pkp 20 pkp 31 pkp 30 pkp 41 pkp 40 pkp 51 pkp 50 pkp 32 pkp 42 pkp 52 pkp 12 pkp 22 pkp 02 positive polarity register nagative polarity register 8 v0 v63 64 prp 01 prp 00 prp 11 prp 10 prp 12 prp 02 pkn 01 pkn 00 pkn 11 pkn 10 pkn 21 pkn 20 pkn 31 pkn 30 pkn 41 pkn 40 pkn 51 pkn 50 pkn 32 pkn 42 pkn 52 pkn 12 pkn 22 pkn 02 prn 01 prn 00 prn 11 prn 10 prn 12 prn 02 grayscale amplifier v1 figure 57: gamma adjustment function
hd66770 rev.1. 1 / april 2002 64 structure of grayscale amplifier indicating structure of the grayscale amplifier as below. determine 8 level (vin0-vin7) by the gradient adjuster and the micro adjustment register. also, dividing these levels with ladder resistors generates v0 to v64 . micro adjustment register (6 x 3 bits) vrp/vrn pkp/n0 3 3 3 3 3 3 3 3 amplitude adjustment register 5 8to1 selector pkp/n1 pkp/n2 pkp/n3 pkp/n4 pkp/n5 prp/n0 prp/n1 gradient adjustment register vdh vgs grayscale amplifier vinp0/vinn0 vinp1/vinn1 vinp2/vinn2 vinp3/vinn3 vinp4/vinn4 vinp5/vinn5 vinp6/vinn6 vinp7/vinn7 v0 v1 v8 v20 v43 v55 v62 v63 v2 v9 v21 v44 v56 v3 v57 ladder resistor 8to1 selector 8to1 selector 8to1 selector 8to1 selector 8to1 selector figure 58: structure of grayscale amplifier reference value adjustment register vdr1/0 2
hd66770 rev.1. 1 / april 2002 65 figure 59: structure of ladder / 8 to 1 selector rp35 rp36 rp37 rp38 vrlp kvp41 kvp42 kvp43 kvp44 kvp45 kvp46 kvp47 kvp48 rp39 rp40 rp41 rp42 rp43 rp44 rp45 kvp49 rp46 vrp rp47 vinp2 prp0[2:0] pkp1[2:0] vinp1 pkp0[2:0] vinp0 vinp3 pkp2[2:0] vinp4 pkp3[2:0] vinp5 pkp4[2:0] vinp6 pkp5[2:0] vinp7 prp1[2:0] vrp1[4:0] rn1 rn2 rn3 rn4 rn5 rn6 rn7 rp1 rp2 rp3 rp4 rp5 rp6 rp7 kvp0 kvp1 kvp2 kvp3 kvp4 kvp5 kvp6 kvp7 kvp8 rp0 vrhp rp9 rp10 kvp9 rp11 rp12 rp13 rp14 rp8 kvp10 kvp11 kvp12 kvp13 kvp14 kvp15 kvp16 rp15 kvp17 kvp18 kvp19 kvp20 kvp21 kvp22 kvp23 kvp24 rp16 rp17 rp18 rp19 rp20 rp21 rp22 rp23 kvp25 kvp26 kvp27 kvp28 kvp29 kvp30 kvp31 kvp32 rp24 rp25 rp26 rp27 rp28 rp29 rp30 rp31 kvp33 kvp34 kvp35 kvp36 kvp37 kvp38 kvp39 kvp40 rp32 rp33 rp34 rn39 rn40 rn41 rn42 rn43 rn44 rn45 kvn49 rn46 vrn rn47 vinn2 prn0[2:0] pkn1[2:0] vinn1 pkn0[2:0] vinn3 pkn2[2:0] vinn4 pkn3[2:0] vinn5 pkn4[2:0] vinn6 pkn5[2:0] vinn7 prn1[2:0] vrn[4:0] kvn1 kvn2 kvn3 kvn4 kvn5 kvn6 kvn7 kvn8 rn0 vrhn rn9 rn10 kvn9 rn11 rn12 rn13 rn14 rn8 kvn10 kvn11 kvn12 kvn13 kvn14 kvn15 kvn16 rn15 kvn17 kvn18 kvn19 kvn20 kvn21 kvn22 kvn23 kvn24 rn16 rn17 rn18 rn19 rn20 rn21 rn22 rn23 kvn25 kvn26 kvn27 kvn28 kvn29 kvn30 kvn31 kvn32 rn24 rn25 rn26 rn27 rn28 rn29 rn30 rn31 kvn33 kvn34 kvn35 kvn36 kvn37 kvn38 kvn39 kvn40 rn32 rn33 rn34 rn35 rn36 rn37 rn38 vrln kvn41 kvn42 kvn43 kvn44 kvn45 kvn46 kvn47 kvn48 4r 5r 16r 5r 5r 8r 0 to 28r 0 to 28r 0 to 31r exvr vdh 5r 4r 1r 1r 1r 1r 4r 5r 16r 5r 5r 8r 0 to 8r 0 to 28r 0 to 31r 5r 4r 1r 1r 1r 1r 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel vdr 0 to 12r
hd66770 rev.1. 1 / april 2002 66 gamma adjustment register this block is the register to set up the grayscale voltage adjusting to the gamma specification of the lcd panel. this register can independent set up to positive/negative polarities and there are four types of register groups to adjust gradient, amplitude, reference-value, and micro-adjustment on number of the grayscale, characteristics of the grayscale voltage. ( using the same setting for reference-value and r.g.b.) following graphics indicates the operation of each adjusting register. 1. gradient adjusting register the gradient-adjusting resistor is to adjust around middle gradient, specification of the grayscale number and the grayscale voltage without changing the dynamic range. to accomplish the adjustment, it controls the variable resistor (vrhp (n) / vrl (n)) of the ladder resistor for the grayscale voltage generator. also, there is an independent resistor on the positive/negative polarities in order for corresponding to as y m metry drive. 2. amplitude adjusting register the amplitude -adjusting resistor is to adjust amplitude of the grayscale voltage. to accomplish the adjustment, it controls the variable resistor (vrp (n)) of the ladder resistor for the grayscale voltage generator located at lower side of the ladder resistor. (adjust upper side by input vdh level.) also, there is an independent resistor on the positive/negative polarities as well as the gradient-adjusting resistor. 3. reference-value adjusting register resister of reference value is to adjust the reference value of grayscale voltage. this function is implemented by controlling the variable resistor (vdr) above the ladder resistor block for grayscale voltage generation. this resistor is common to both the positive and negative. figure 61 amplitude adjustment grayscale number grayscale voltage grayscale voltage grayscale number figure 60 gradient adjustment grayscale voltage grayscale number figure 62 reference-value adjustment grayscale number figure 63 micro-adjustment grayscale voltage
hd66770 rev.1. 1 / april 2002 67 4. micro-adjusting register the micro-adjusting register is to make subtle adjustment of the grayscale voltage level. to accomplish the adjustment, it controls the each reference voltage level by the 8 to 1 selector towards the 8-leveled reference voltage generated from the ladder resistor. also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors. table 36: output signal list 8 to 1 selector voltage level for the grayscale 1 pkp0[2:0] pkn0[2:0] set-up contents for positive polarity for negative polarity pkp1[2:0] pkn1[2:0] pkp2[2:0] pkn2[2:0] pkp3[2:0] pkn3[2:0] pkp4[2:0] pkn4[2:0] pkp5[2:0] pkns5[2:0] prp0[2:0] prn0[2:0] prp1[2:0] prn1[2:0] variable resistor vr ?g?o ?i?m?j variable resistor vr ?k?o ?i?m?j resistor classification micro- adjustment gradient adjustment vrp[4:0] vrn[4:0] variable resistor ?u?q?o ?i?m?j amplitude adjustment 8 to 1 selector voltage level for the grayscale 8 8 to 1 selector voltage level for the grayscale 20 8 to 1 selector voltage level for the grayscale 43 8 to 1 selector voltage level for the grayscale 55 8 to 1 selector voltage level for the grayscale 62 reference-value adjustment v dr [1:0] variable resistor vdr
hd66770 rev.1. 1 / april 2002 68 ladder resistor / 8 to 1 selector block configuration this block outputs the reference voltage of the grayscale voltage. there are two ladder resistors including the variable resistor and the 8 to 1 selector selecting voltage generated by the ladder resistor. the gamma registers control the variable resistors and 8 to 1 selector resistors . also, there are pins that connect to the external variable resistor. and it allows compensating the dispersion of length between one panel to another. variable resistor there are 3 types of the variable resistors that is for the gradient adjustment (vrhp (n) / vrlp (n)), for the amplitude adjustment (vrp (n)), and for the reference-value adjustment (vdr). the ohmic value is set by the gradient adjusting resistor, the amplitude-adjusting resistor, and the reference-value adjusting resistor as below. table 37: gradient adjustment table 38: amplitude adjustment table 39: reference-value adjustment register value prp (n) [2.0] resistance value vrp (n) register value vrp (n) [4.0] resistance value vrp (n) register value vdr [1.0] resistance value vdr 000 0r 00000 0r 00 0r 001 4r 00001 1r 01 4r 010 8r 00010 2r 10 8r 011 12r 11 12r 101 20r 110 24r 11101 29r 111 28r 11110 30r 11111 31r the 8 to 1 selector in the 8 to 1 selector, the voltage level can be selected from the levels which are generated by ladder resistors. and output the six types of the reference voltage, the vin1- to vin6. following figure explains the relationship between the micro-adjusting register and the selecting voltage. register value selected voltage pkp (n) [2:0] vinp (n) 1 vinp (n) 2 vinp (n) 3 vnip (n) 4 vnip (n) 5 vinp (n) 6 000 kvp (n) 1 kvp (n) 9 kvp (n) 17 kvp (n) 25 kvp (n) 33 kvp (n) 41 001 kvp (n) 2 kvp (n) 10 kvp (n) 18 kvp (n) 26 kvp (n) 34 kvp (n) 42 010 kvp (n) 3 kvp (n) 11 kvp (n) 19 kvp (n) 27 kvp (n) 35 kvp (n) 43 011 kvp (n) 4 kvp (n) 12 kvp (n) 20 kvp (n) 28 kvp (n) 36 kvp (n) 44 100 kvp (n) 5 kvp (n) 13 kvp (n) 21 kvp (n) 29 kvp (n) 37 kvp (n) 45 101 kvp (n) 6 kvp (n) 14 kvp (n) 22 kvp (n) 30 kvp (n) 38 kvp (n) 46 110 kvp (n) 7 kvp (n) 15 kvp (n) 23 kvp (n) 31 kvp (n) 39 kvp (n) 47 111 kvp (n) 8 kvp (n) 16 kvp (n) 24 kvp (n) 32 kvp (n) 40 kvp (n) 48 table 40
hd66770 rev. 1.1 / april 2002 69 table 38 voltage formula: positive formula pins ?u?c?g?|? v*5r/sumrp micro-adjusting register value kvp0 kvp1 kvp2 kvp3 kvp4 kvp5 kvp6 kvp7 kvp8 kvp9 kvp10 kvp11 kvp12 kvp13 kvp14 kvp15 kvp16 kvp17 kvp18 kvp19 kvp20 kvp21 kvp22 kvp23 kvp24 kvp25 kvp26 kvp27 kvp28 kvp29 kvp30 kvp31 kvp32 kvp33 kvp34 kvp35 kvp36 kvp37 kvp38 kvp39 kvp40 kvp41 kvp42 kvp43 kvp44 kvp45 kvp46 kvp47 ?u?c?g?|? v*9r/sumrp ?u?c?g?|? v*13r/sumrp ?u?c?g?|? v*17r/sumrp ?u?c?g?|? v*21r/sumrp ?u?c?g?|? v*25r/sumrp ?u?c?g?|? v*29r/sumrp ?u?c?g?|? v*33r/sumrp ?u?c?g?|? v*(33r+vrhp)/sumrp ?u?c?g?|? v*(34r+vrhp)/sumrp ?u?c?g?|? v*(35r+vrhp)/sumrp ?u?c?g?|? v*(36r+vrhp)/sumrp ?u?c?g?|? v*(37r+vrhp)/sumrp ?u?c?g?|? v*(38r+vrhp)/sumrp ?u?c?g?|? v*(39r+vrhp)/sumrp ?u?c?g?|? v*(52r+vrhp)/sumrp ?u?c?g?|? v*(40r+vrhp)/sumrp ?u?c?g?|? v*(45r+vrhp)/sumrp ?u?c?g?|? v*(46r+vrhp)/sumrp ?u?c?g?|? v*(47r+vrhp)/sumrp ?u?c?g?|? v*(48r+vrhp)/sumrp ?u?c?g?|? v*(49r+vrhp)/sumrp ?u?c?g?|? v*(50r+vrhp)/sumrp ?u?c?g?|? v*(51r+vrhp)/sumrp ?u?c?g?|? v*(68r+vrhp)/sumrp ?u?c?g?|? v*(69r+vrhp)/sumrp ?u?c?g?|? v*(70r+vrhp)/sumrp ?u?c?g?|? v*(71r+vrhp)/sumrp ?u?c?g?|? v*(72r+vrhp)/sumrp ?u?c?g?|? v*(73r+vrhp)/sumrp ?u?c?g?|? v*(74r+vrhp)/sumrp ?u?c?g?|? v*(75r+vrhp)/sumrp ?u?c?g?|? v*(80r+vrhp)/sumrp ?u?c?g?|? v*(81r+vrhp)/sumrp ?u?c?g?|? v*(82r+vrhp)/sumrp ?u?c?g?|? v*(83r+vrhp)/sumrp ?u?c?g?|? v*(84r+vrhp)/sumrp ?u?c?g?|? v*(85r+vrhp)/sumrp ?u?c?g?|? v*(86r+vrhp)/sumrp ?u?c?g?|? v*(87r+vrhp)/sumrp ?u?c?g?|? v*(87r+vrhp+vrlp)/sumrp ?u?c?g?|? v*(91r+vrhp+vrlp)/sumrp ?u?c?g?|? v*(95r+vrhp+vrlp)/sumrp ?u?c?g?|? v*(99r+vrhp+vrlp)/sumrp ?u?c?g?|? v*(103r+vrhp+vrlp)/sumrp ?u?c?g?|? v*(107r+vrhp+vrlp)/sumrp ?u?c?g?|? v*(111r+vrhp+vrlp)/sumrp vdh *r - pkp02-00 = "000" kvp48 ?u?c?g?|? v*(115r+vrhp+vrlp)/sumrp kvp49 ?u?c?g?|? v*(120r+vrhp+vrlp)/sumrp pkp02-00 = "001" pkp02-00 = "010" pkp02-00 = "011" pkp02-00 = "100" pkp02-00 = "101" pkp02-00 = "110" pkp02-00 = "111" pkp12-10 = "000" pkp12-10 = "001" pkp12-10 = "010" pkp12-10 = "011" pkp12-10 = "100" pkp12-10 = "101" pkp12-10 = "110" pkp12-10 = "111" pkp22-20 = "000" pkp22-20 = "001" pkp22-20 = "010" pkp22-20 = "011" pkp22-20 = "100" pkp22-20 = "101" pkp22-20 = "110" pkp22-20 = "111" pkp32-30 = "000" pkp32-30 = "001" pkp32-30 = "010" pkp32-30 = "011" pkp32-30 = "100" pkp32-30 = "101" pkp32-30 = "110" pkp32-30 = "111" pkp42-40 = "000" pkp42-40 = "001" pkp42-40 = "010" pkp42-40 = "011" pkp42-40 = "100" pkp42-40 = "101" pkp42-40 = "110" pkp42-40 = "111" pkp52-50 = "000" pkp52-50 = "001" pkp52-50 = "010" pkp52-50 = "011" pkp52-50 = "100" pkp52-50 = "101" pkp52-50 = "110" pkp52-50 = "111" - reference voltage vinp0 vinp1 vinp2 vinp3 vinp4 vinp5 vinp6 vinp7 r: {[(sumrp*sumrn)/(sumrp+sumrn)]+exvr}/{ vdr+[(sumrp*sumrn)/(sumrp+sumrn)] +exvr} sumrp: total of the positive polarity ladder resistance = 128 r + vrhp + vrlp + vrp sumrn: total of the negative polarity ladder resistance = 128 r + vrln + vrn ? v: voltage difference between kv0 to kv49 period ?? vdh*sumrp*sumrn / [sumrp*sumrn+exvr*(sumrp+sumrn)] table 41
hd66770 rev. 1.1 / april 2002 70 table 42 : voltage formula (positive polarity) formula v0 vinn0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v32 v33 v34 v35 v36 v37 v38 v39 v40 v41 v42 v43 v44 v45 v46 v47 v48 v49 v50 v51 v52 v53 v54 v55 v56 v57 v58 v59 v60 v61 v62 v63 vinn1 vinn3 vinn4 vinn7 vinn6 v8+(v1-v8)*(450/800) v3+(v1-v3)*(8/24) v8+(v3-v8)*(16/24) v8+(v3-v8)*(12/24) v8+(v3-v8)*(8/24) v8+(v3-v8)*(4/24) v20+(v8-v20)*(22/24) v20+(v8-v20)*(20/24) v20+(v8-v20)*(18/24) v20+(v8-v20)*(16/24) v20+(v8-v20)*(14/24) v20+(v8-v20)*(12/24) v20+(v8-v20)*(10/24) v20+(v8-v20)*(8/24) v20+(v8-v20)*(6/24) v20+(v8-v20)*(4/24) v20+(v8-v20)*(2/24) v43+(v20-v43)*(22/23) v43+(v20-v43)*(21/23) v43+(v20-v43)*(20/23) v43+(v20-v43)*(19/23) v43+(v20-v43)*(18/23) v43+(v20-v43)*(17/23) v43+(v20-v43)*(16/23) v43+(v20-v43)*(15/23) v43+(v20-v43)*(14/23) v43+(v20-v43)*(13/23) v43+(v20-v43)*(12/23) v43+(v20-v43)*(11/23) v43+(v20-v43)*(10/23) v43+(v20-v43)*(9/23) v43+(v20-v43)*(8/23) v43+(v20-v43)*(7/23) v43+(v20-v43)*(6/23) v43+(v20-v43)*(5/23) v43+(v20-v43)*(4/23) v43+(v20-v43)*(3/23) v43+(v20-v43)*(2/23) v43+(v20-v43)*(1/23) v55+(v43-v55)*(22/24) v55+(v43-v55)*(20/24) v55+(v43-v55)*(18/24) v55+(v43-v55)*(16/24) v55+(v43-v55)*(14/24) v55+(v43-v55)*(12/24) v55+(v43-v55)*(10/24) v55+(v43-v55)*(8/24) v55+(v43-v55)*(6/24) v55+(v43-v55)*(4/24) v55+(v43-v55)*(2/24) v62+(v55-v62)*(350/800) v60+(v55-v60)*(20/24) v60+(v55-v60)*(16/24) v60+(v55-v60)*(12/24) v60+(v55-v60)*(8/24) v62+(v60-v62)*(16/24) vinp vinp5 note: keep the relation below ddvdh-v8>1-1v v55-gnd>1-1v
hd66770 rev. 1.1 / april 2002 71 table 43: voltage formula (negative polarity) table 40 voltage formula: negative polarity r: {[(sumrp*sumrn)/(sumrp+sumrn)]+exvr}/{ vdr+[(sumrp*sumrn)/(sumrp+sumrn)] +exvr} sumrp: total of the positive polarity ladder resistance = 128 r + vrhp + vrlp + vrp sumrn: total of the negative polarity ladder resistance = 128 r + vrln + vrn ? v: voltage difference between kv0 to kv49 period ?? vdh*sumrp*sumrn / [sumrp*sumrn+exvr*(sumrp+sumrn)] formula pins ?u?c?g?|? v*5r/sumrn kvn0 kvn1 kvn2 kvn3 kvn4 kvn5 kvn6 kvn7 kvn8 kvn9 kvn10 kvn11 kvn12 kvn13 kvn14 kvn15 kvn16 kvn17 kvn18 kvn19 kvn20 kvn21 kvn22 kvn23 kvn24 kvn25 kvn26 kvn27 kvn28 kvn29 kvn30 kvn31 kvn32 kvn33 kvn34 kvn35 kvn36 kvn37 kvn38 kvn39 kvn40 kvn41 kvn42 kvn43 kvn44 kvn45 kvn46 kvn47 ?u?c?g?|? v*9r/sumrn ?u?c?g?|? v*13r/sumrn ?u?c?g?|? v*17r/sumrn ?u?c?g?|? v*21r/sumrn ?u?c?g?|? v*25r/sumrn ?u?c?g?|? v*29r/sumrn ?u?c?g?|? v*33r/sumrn ?u?c?g?|? v*(33r+vrhn)/sumrn ?u?c?g?|? v*(34r+vrhn)/sumrn ?u?c?g?|? v*(35r+vrhn)/sumrn ?u?c?g?|? v*(36r+vrhn)/sumrn ?u?c?g?|? v*(37r+vrhn)/sumrn ?u?c?g?|? v*(38r+vrhn)/sumrn ?u?c?g?|? v*(39r+vrhn)/sumrn ?u?c?g?|? v*(52r+vrhn)/sumrn ?u?c?g?|? v*(40r+vrhn)/sumrn ?u?c?g?|? v*(45r+vrhn)/sumrn ?u?c?g?|? v*(46r+vrhn)/sumrn ?u?c?g?|? v*(47r+vrhn)/sumrn ?u?c?g?|? v*(48r+vrhn)/sumrn ?u?c?g?|? v*(49r+vrhn)/sumrn ?u?c?g?|? v*(50r+vrhn)/sumrn ?u?c?g?|? v*(51r+vrhn)/sumrn ?u?c?g?|? v*(68r+vrhn)/sumrn ?u?c?g?|? v*(69r+vrhn)/sumrn ?u?c?g?|? v*(70r+vrhn)/sumrn ?u?c?g?|? v*(71r+vrhn)/sumrn ?u?c?g?|? v*(72r+vrhn)/sumrn ?u?c?g?|? v*(73r+vrhn)/sumrn ?u?c?g?|? v*(74r+vrhn)/sumrn ?u?c?g?|? v*(75r+vrhn)/sumrn ?u?c?g?|? v*(80r+vrhn)/sumrn ?u?c?g?|? v*(81r+vrhn)/sumrn ?u?c?g?|? v*(82r+vrhn)/sumrn ?u?c?g?|? v*(83r+vrhn)/sumrn ?u?c?g?|? v*(84r+vrhn)/sumrn ?u?c?g?|? v*(85r+vrhn)/sumrn ?u?c?g?|? v*(86r+vrhn)/sumrn ?u?c?g?|? v*(87r+vrhn)/sumrn ?u?c?g?|? v*(87r+vrhn+vrln)/sumrn ?u?c?g?|? v*(91r+vrhn+vrln)/sumrn ?u?c?g?|? v*(95r+vrhn+vrln)/sumrn ?u?c?g?|? v*(99r+vrhn+vrln)/sumrn ?u?c?g?|? v*(103r+vrhn+vrln)/sumrn ?u?c?g?|? v*(108r+vrhn+vrln)/sumrn ?u?c?g?|? v*(111r+vrhn+vrln)/sumrn vdh *r kvn48 kvn49 ?u?c?g?|? v*(115r+vrhn+vrln)/sumrn ?u?c?g?|? v*(120r+vrhn+vrln)/sumrn micro-adjusting register value - pkn02-00 = "000" pkn02-00 = "001" pkn02-00 = "010" pkn02-00 = "011" pkn02-00 = "100" pkn02-00 = "101" pkn02-00 = "110" pkn02-00 = "111" pkn12-10 = "000" pkn12-10 = "001" pkn12-10 = "010" pkn12-10 = "011" pkn12-10 = "100" pkn12-10 = "101" pkn12-10 = "110" pkn12-10 = "111" pkn22-20 = "000" pkn22-20 = "001" pkn22-20 = "010" pkn22-20 = "011" pkn22-20 = "100" pkn22-20 = "101" pkn22-20 = "110" pkn22-20 = "111" pkn32-30 = "000" pkn32-30 = "001" pkn32-30 = "010" pkn32-30 = "011" pkn32-30 = "100" pkn32-30 = "101" pkn32-30 = "110" pkn32-30 = "111" pkn42-40 = "000" pkn42-40 = "001" pkn42-40 = "010" pkn42-40 = "011" pkn42-40 = "100" pkn42-40 = "101" pkn42-40 = "110" pkn42-40 = "111" pkn52-50 = "000" pkn52-50 = "001" pkn52-50 = "010" pkn52-50 = "011" pkn52-50 = "100" pkn52-50 = "101" pkn52-50 = "110" pkn52-50 = "111" - reference voltage vinn0 vinn1 vinn2 vinn3 vinn4 vinn5 vinn6 vinn7
hd66770 rev. 1.1 / april 2002 72 table 44 voltage formula (negative polarity) formula v0 vinn0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v32 v33 v34 v35 v36 v37 v38 v39 v40 v41 v42 v43 v44 v45 v46 v47 v48 v49 v50 v51 v52 v53 v54 v55 v56 v57 v58 v59 v60 v61 v62 v63 vinn1 vinn2 vinn3 vinn4 vinn5 vinn7 vinn6 v8+(v1-v8)*(450/800) v3+(v1-v3)*(8/24) v8+(v3-v8)*(16/24) v8+(v3-v8)*(12/24) v8+(v3-v8)*(8/24) v8+(v3-v8)*(4/24) v20+(v8-v20)*(22/24) v20+(v8-v20)*(20/24) v20+(v8-v20)*(18/24) v20+(v8-v20)*(16/24) v20+(v8-v20)*(14/24) v20+(v8-v20)*(12/24) v20+(v8-v20)*(10/24) v20+(v8-v20)*(8/24) v20+(v8-v20)*(6/24) v20+(v8-v20)*(4/24) v20+(v8-v20)*(2/24) v43+(v20-v43)*(22/23) v43+(v20-v43)*(21/23) v43+(v20-v43)*(20/23) v43+(v20-v43)*(19/23) v43+(v20-v43)*(18/23) v43+(v20-v43)*(17/23) v43+(v20-v43)*(16/23) v43+(v20-v43)*(15/23) v43+(v20-v43)*(14/23) v43+(v20-v43)*(13/23) v43+(v20-v43)*(12/23) v43+(v20-v43)*(11/23) v43+(v20-v43)*(10/23) v43+(v20-v43)*(9/23) v43+(v20-v43)*(8/23) v43+(v20-v43)*(7/23) v43+(v20-v43)*(6/23) v43+(v20-v43)*(5/23) v43+(v20-v43)*(4/23) v43+(v20-v43)*(3/23) v43+(v20-v43)*(2/23) v43+(v20-v43)*(1/23) v55+(v43-v55)*(22/24) v55+(v43-v55)*(20/24) v55+(v43-v55)*(18/24) v55+(v43-v55)*(16/24) v55+(v43-v55)*(14/24) v55+(v43-v55)*(12/24) v55+(v43-v55)*(10/24) v55+(v43-v55)*(8/24) v55+(v43-v55)*(6/24) v55+(v43-v55)*(4/24) v55+(v43-v55)*(2/24) v62+(v55-v62)*(350/800) v60+(v55-v60)*(20/24) v60+(v55-v60)*(16/24) v60+(v55-v60)*(12/24) v60+(v55-v60)*(8/24) v62+(v60-v62)*(16/24) note: keep the relation below ddvdh-v8>1-1v v55-gnd>1-1v
hd66770 rev.1.1 / april 2002 73 figure 65: relationship between source output and vcom negative positive polarity sn vcom relationship between ram data and output figure 6 4 : relationship between ram data and output ram output level v0 v63 negative positive polarity db15-11, 4- ?f 00000 db10-5 ?f 000000 db15-11, 4- ?f 11111 db10-5 ?f 111111
hd66770 rev.1.1 / april 2002 74 the 8-color display mode the hd66770 carries 8-color display mode. using grayscale levels are v0 and v63 and all other level power supplies are halt. so that it attempts to lower power consumption. also, during the 8-color mode, the gamma micro adjustment register, pkp00-pkp52 and pkn00-pkn52 are invalid. rewrite the data of gram r/b to 00000 or 11111, g to 000000 or 111111 before set the mode in order to select v0/v63. the level power supply (v1-v62) is in off condition during the 8-color mode. r 3 r 2 r 1 g 2 g 1 g 0 b 3 b 2 display data msb lsb graphics ram (gram) r 0 g 3 b 1 b 0 b 4 g 4 g 5 r 4 on/off control on/off control on/off control 5 6 5 lcd driver lcd driver lcd dr i ver r g b lcd pkp 01 pkp 00 pkp 11 pkp 10 pkp 21 pkp 20 pkp 31 pkp 30 pkp 41 pkp 40 pkp 51 pkp 50 pkp 32 pkp 42 pkp 52 pkp 12 pkp 22 pkp 02 positive polarity register negative polarity register 8 v0 v63 2 prp 01 prp 00 prp 11 prp 10 prp 12 prp 02 pkn 01 pkn 00 pkn 11 pkn 10 pkn 21 pkn 20 pkn 31 pkn 30 pkn 41 pkn 40 pkn 51 pkn 50 pkn 32 pkn 42 pkn 52 pkn 12 pkn 22 pkn 02 prn 01 prn 00 prn 11 prn 10 prn 12 prn 02 grayscale amplifier figure 6 6 : grayscale control
hd66770 rev.1.1 / april 2002 75 65536 color -> 8 colors ram set up transfer serials off gon ="1" dte ="1" d1-0="10" wait (2 frames or longer) on gon ="1" dte ="0" d1-0="10" off gon ="0" dte ="0" d1-0="00" on gon ="0" dte ="0" d1-0="01" on gon ="1" dte ="0" d1-0="01" on gon ="1" dte ="0" d1-0="11" on gon ="1" dte ="1" d1-0="11" display by 8-color mode cl="1" wait ( 4 0ms or longer) wait (2 frames or longer) wait (2 frames or longer) transfer serials wait (2 h period or longer) 8 colors -> 65536 colors on gon ="1" dte ="1" d1-0="10" off gon ="1" dte ="0" d1-0="10" off gon ="0" dte ="0" d1-0="00" on gon ="0" dte ="0" d1-0="01" on gon ="1" dte ="0" d1-0="01" on gon ="1" dte ="0" d1-0="11" on gon ="1" dte ="1" d1-0="11" display by 65536-color mode cl="0" wait (2 frames or longer) wait (2 frames or longer) transfer serials ram set up wait ( 4 0ms or longer) wait (2 frames or longer) transfer serials wait (2 h period or longer) figure 67
hd66770 rev.1.1 / april 2002 76 example of system configuration following diagram indicates the system structure, which composes the 132 (horizontal) x 176 (vertical) dot tft-lcd panel. this must be used together with the gate driver ; hd66771 and the power supply ic; hd667p00. figure 64: example of tft display system 176 hd66771 hd66770 db0 to db15 cs*, wr*, rd*, rs cl1, flm, disptmg 132 pixel x 3 s2 s396 s395 s1 g1 g176 g2 g175 tft-lcd 3 gcs*, gda, gcl 4 3 hd667p00 vgh, vgl, vgoff vdh (v0 to v15 power supply for generator) vcom m, eq vcom reset dcclk im2, im1 ,im0/id 3 2 ddvdh (power supply for liquid crystal output) reset gcs*, gda ,gcl cl1, flm , disptmg reset vcc gnd vcc gnd vcc, vci1, vci gnd figure 68 16
hd66770 rev.1.1 / april 2002 77 setting of the vcom voltage changes connecting method . following diagram indicates a connection example of the hd66771 and hd667p00 when vcoml < 0v, 0v <= vcoml < 5.5v. cl1 flm gcs* gcl gda vgl vgh vgoff cl1 flm gcs* gcl gda vdh hd66771 hd6677 0 dcclk hd667p00 vgh vgl vdh m eq vcomr to tft panel common electrode vcc ,vci , vci4 gnd vreg1out vreg1 vreg2out vreg2 vcc gnd open vcom *1) *1) *2) *2) *3) *3) * 7 ) *3) *3 ) * 9 ) *3 ) *3) disptmg *3) ddvdh * 9 ) *5) * 9 ) *5) disptmg *1) vcc gnd *6) vgl vlout1 vlout2 vcom vgoff vlout3 vdh dcclk m eq gcs* gcl gda ddvdh vgh vcomh vcoml vgoffh vgoffl vciout vci1 *2) vlout4 vcl vci2 vci3 open v0 v1n v1p v3p v60n v60p v3n *7) * ?v?j v61p v62n v62p v61n *7) *1) vcc and gnd must be equivalence to input to hd66770, hd66771 and hd667p0 0 . *2) open the vcom and eq pins of hd66770. eq pins of hd667p0 must be gnd. *3) use the 1uf condenser with the b property when it is connected in the stabilized capacity. *5) supply voltage of 2.5v to 3.3v to vci with the external power supply. and supply voltage of 2.5v to 3.3v to vci1 or for connecting vciout and vci1 with the external power supply. *4) condensers connected to following terminals of hd667p00 are omitted . c11 to c12-, c11+ to c12+, c21- to c23-, c21+ to c23+, c31-, c31+, c41-, c41+ for these connections of condensers, connections refer to function of the hd667p00 pins to connect. *6) connect the shot key barrier diode, which contains approx. vf = 0.3 v/1ma and vr >= 30v. *7) use the condenser of 0.1uf with the b property when it is connected in the stabilized capacity. figure 6 9 : connection example of hd66770 and hd66771 (when vcoml < 0v) * 8 ) * 10 ) *3) *8 ) connect the 0.1 f capacitor (b characteristics) as a capacitor for stabilization according to the display quality and power consumption. *9 ) when step-up circuit 4, vcoml and vgoffh are used, use the 1- f capacitor (b characteristics) according to the setting mode. when they are not used, leave the pin open. *10 ) use a vaiable resistor more than 200k w .
hd66770 rev.1.1 / april 2002 78 following diagram indicates a connection example of the gate driver, hd66771 and power supply ic when 0 <= vcoml < 5.5, and using equalizing function. *1) cl1 flm gcs* gcl gda vdh hd66770 dcclk vgl vdh m eq vcom *2) *2) *3) *7) *3) * 9) *3) vgl vlout1 vlout2 hd667p00 vcom vlout3 dcclk m eq gcs* gcl gda ddvdh vgh vcomr vcomh vcoml vcc ,vci , vci4 gnd vciout vci1 vreg1out vreg1 vreg2out vreg2 *2) *3) vgoff vgoffh vgoffl *3) * 9 ) vlout4 vcl * 9 ) *5) disptmg *3) ddvdh vcc gnd *1) cl1 flm gcs* gcl gda vgl vgh vgoff hd66771 disptmg vcc gnd *6) vci2 *1) vgh *3) vci3 v0 v1n v1p v3p v60n v60p v3n *7) *7) v61p v62n v62p v61n *7) to tft panel opposite electrode figure 70: connection example of hd66770 and hd66771 (when 0v <= vcoml< 5.5v) * 8 ) * 10 ) testa4 testa3 testa2 testa1 *5) *3 ) vdh *1) vcc and gnd must be equivalence to input to hd66770, hd66771 and hd667p00. *2) connect eq pins of hd66770 and eq pins of hd667p00. connect vcom pins to vcom pins of the hd667p00. also, do not use when vcom voltage is 5.5v or higher. *3) use the 1ufcondenser with the b property when it is connected in the stabilized capacity. *4) condensers connected to following terminals of hd667p00 are omitted. c11- to c12-, c11+ to c12+, c21- to c23-, c21+ to c23-, c31-, c31+, c41-, c41+ for these connections of condensers, refer to function of the hd667p00 pins to connect. *5) supply voltage of 2.5v to 3.3v to vci with the external power supply. and supply voltage 2.5v to 3.3v to vci 1 for connecting vciout and vci1 with the external power supply. when vci1 is connecting to the external power supply, leave vciout open. *6) connect the schotkey barrier diode, which contains approx. vf = 0.3 v/1ma and vr>= 30v. *7) use the condenser of 0.1uf with the b property when it is connected in the stabilized capacity. *8 ) connect the 0.1 f capacitor (b characteristics) as a capacitor for stabilization according to the display quality and power consumption. *9 ) when step-up circuit 4, vcoml and vgoffh are used, use the 1- f capacitor (b characteristics) according to the setting mode. when they are not used, leave the pin open. *10 ) use a variable resistor more than 200k w .
hd66770 rev.1.1 / april 2002 79 specification of capacitor connected to hd66770 and hd667p00 the following table indicates the specification of capacitor connected to hd66770 and hd667p00. product capacity of capacitor recommendation resist pressure for capacitor connect pins 6v veg1out, vciout, c41-/+*1, vlout4*1, vcomh*1, vcoml 10v vlout1, c11-/+, c12-/+, c21-/+, c22-/+, c23-/+ 1 m f (b character) 25v vreg2out. vlout2, vlout3, c31-/+, vgoffh*1, vgoffl 6v vdh, (testa1)*2, (testa2)* 2 , regp*2, regn* 2 hd667p00 0.1 m f (b character) 25v (testa3), (testa4) hd66770 0.1 m f (b character) 6v v0, v1p, v1n, v3p, v3n, v60p, v60n, v62p, v62n, v63p, v63n *1 according to the mode set hd667p00, there is some cases in which capacitor is unnecessary. *2 connect a capacitor to stabilize picture. be noticed that power consumption may rise in great amount.
hd66770 rev.1.1 / april 2002 80 instruction setting flow when the hd66771/hd667p00 are used, follow the instruction setting flow. the instruction setting for the hd66771/hd667p00 is executed by the serial interface. when the instruction for the hd66771/hd667p00 is set, the serial transfer must be executed to the hd66771/hd667p00. the transfer to the hd66771/hd667p00 must be executed immediately after the instruction set. follow the below serial transfer flow about each setting and then transfer must be executed. note: for more information on the flow for power settings, refer to the hd667p00 data sheet. power setting display on gon ="0" dte ="0" d1-0="01" wait (more than 2 frames) display on gon ="1" dte ="0" d1-0="01" serial transfer display on gon ="1" dte ="0" d1-0="11" display on gon ="1" dte ="1" d1-0="11" display on continue to the display off flow. wait ( more than 2 h period ) figure 71 serial transfer display off display off gon ="1" dte ="1" d1-0="10" wait (more than 2 frames) display off gon ="1" dte ="0" d1-0="10" display off gon ="0" dte ="0" d1-0="00" power off sap2-0="000" ap2-0 ="000" continue to the display on flow. serial transfer eq = 0
hd66770 rev.1.1 / april 2002 81 standby set (stb = " 1 " ) oscillation start standby cancel (stb = ? 0 ? ) wait 10 ms standby set standby cancel power setting display off flow display on flow sleep set (slp = ? 1 ? ) sleep cancel (slp = ? 0 ? ) sleep set power setting display off flow serial transfer display on flow sleep cancel serial transfer note: for more information on the flow for power settings, refer to the hd667p00 data sheet. figure 72
hd66770 rev.1.1 / april 2002 82 oscillation circuit the hd66770 can oscillate between the osc1 and osc2 pins using an internal r-c oscillator with an external oscillation resistor. note that in r-c oscillation, the oscillation frequency is changed according to the external resistance value, wiring length, or operating power-supply voltage. if rf is increased or power supply voltage is decrease, the oscillation frequency decreases. for the relationship between rf resistor value and oscillation frequency, see the electric characteristics notes section. 1) external clock mode osc1 osc2 clock hd66770 damping resistance (2k ?? ) 2) external resistance oscillation mode rf osc1 osc2 hd66770 note: the rf resistance must be located n ear the osc1/osc2 pin on the master side . figure 73: oscillation circuits
hd66770 rev.1.1 / april 2002 83 n-raster-row reversed ac drive the hd66770 supports not only the lcd reversed ac drive in a one-frame unit but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from one to 64 raster-rows. when a problem affecting display quality occurs, the n-raster-row reversed ac drive can improve the quality. determine the number of the raster-rows n (nw bit set value +1) for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-row is reduced, the lcd alternating frequency becomes high. because of this, the charge or discharge current is increased in the lcd cells. 1 2 3 184 frame a/c wave - form drive 176 raster-row n-raster-row a/c wave - form drive 176 raster-row reverse 3 raster-row eor="1" 1 frame 1 frame 1 2 3 176 184 176 blank period blank period 1 2 4 4 175 175 note: in an n-raster-row driving eor should be ? 1 ? so that dc bias voltage is not applied . figure74: example of an ac signal under n-raster-row reversed ac drive
hd66770 rev.1.1 / april 2002 84 interlace drive hd66770 supports the interlace drive to protect from the display flicker. it splits one frame into n fields and drives. determine the n fields (fld bit stetting value) after confirming on the actual lcd display. following table indicates n fields: the gate selecting position when it is 1 or 3. and the diagram below indicates the output waveform when the 3-field interlace drive is active. figure 75: gate output timing on the 3 field interlace ac polarity g1 g2 g3 g4 g5 g6 1 frame field (1) field (2) field (3) field (1) g3n+1 g3n+2 g3n+3 blank period gs = "0" gs = "1" fld1-0 : setting value g1 g2 g3 g4 g5 g6 g7 g8 g174 g9 g175 g176 field gate - 01 11 (1) (2) (3) ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? g173 ?? ?? ?? ?? fld1-0 : setting value g228 g227 g226 g225 g224 g223 g222 g221 g55 g220 g54 g53 field gate - 01 11 (1) (2) (3) ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? g56 ?? ?? ?? ?? table 45
hd66770 rev.1.1 / april 2002 85 ac drive timing following diagram indicates the timing of changing polarity on the each a/c drive method. lcd drive polarity is changed after every frame. after the a/c t his timing , the blank (all outputs from the gate: vgoff output) in 8h period is inserted. also, lcd drive polarity is change after every field when it is on the interlace drive and a blank is inserted in every timing. the amount of blanking periods becomes 16h in a frame. when the reversed n- raster-row is driving, a blank period of the 8h period is inserted after all screens are drawn n-raster-row reversed ac drive changing polarity frame reverse ac drive frame 1 blank period blank period = 8h period a/c 3 field interlace drive field 1 field 3 field 2 blank period 1 blank period 2 blank period 3 a/c a/c blank period = blank period 1 + blank period 2 + blank period 3 =8h period n-raster-row blank period blank period =8h period 1 frame period 1 frame period 1 frame period a/c a/c a/c a/c a/c a/c a/c a/c a/c a/c a/c a/c n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row figure 76
hd66770 rev.1.1 / april 2002 86 frame frequency adjusting function the hd66770 has an on-chip frame-frequency adjustment function. the frame frequency can be adjusted by the instruction setting (div, rtn) during the lcd driver as the oscillation frequency is always same. if the oscillation frequency is set to high, animation or a static image can be displayed in suitable ways by changing the frame frequency. when a static image is displayed, the frame frequency can be set low and the low-power consumption mode can be entered. when high-speed screen switching for an animated display, etc. is required, the frame frequency can be set high. relationship between lcd drive duty and frame frequency the relationship between the lcd drive duty and the frame frequency is calculated by the following expression. the frame frequency can be adjusted in the 1h period adjusting bit (rtn) and in the operation clock division bit (div) by the instruction. example of calculation in case of maximum frame frequency = 60 hz; driver raster-row: 176 1h period: 16 clock (rtn3 to 0 = ? 0000 ? ) operation clock division ratio: 1 division fosc = 60hz x (0+16) clock x 1 division x (176+8) lines = 177 [khz] in this case, the cr oscillation frequency becomes 177 khz. the external resistance value of the r-c oscillator must be adjusted to be 177 khz. frame frequency = fosc clock cycles per raster-row x division ratio x (line+8) [hz] fosc : r-c oscillation frequency line : numbers of raster-rows (nl bit) clock cycles per raster-row: rtn bit division ratio: div bit (formula for the frame frequency)
hd66770 rev.1.1 / april 2002 87 screen-division driving function the hd66770 can select and drive two screens at any position with the screen-driving position registers (r14 and r15). any two screens required for display are selectively driven and reducing lcd-driving voltage and power consumption. for the 1 st division screen, start lines (ss17 to 10) and end lines (se17 to 10) are specified by the 1 st screen-driving position register (r14). for the 2 nd division screen, start line (ss27 to 20) and end lines (se27 to 20) are specified by the 2 nd screen-driving position register (r15). the 2 nd screen control is effective when the spt bit is 1. the total count of selection-driving lines for the 1 st and 2 nd screens must be the number of lcd drive raster-rows or less. driving on 2 screen s figure 77: display example in 2-screen division driving driving raster- r o w : nl4-0 = "10101" (176 lines) 1st screen setting: ss17-10 = "00"h, se17-10 = "06"h 2nd screen setting: ss27-20 = "19"h, se27-20 = "29"h, spt = "1" g1 g26 g7 g42 non-display area 1st screen: 7 raster-row driving 2nd screen: 17 raster-row driving non-display area
hd66770 rev.1.1 / april 2002 88 restrictions on the 1 st /2 nd screen driving position register settings the following restrictions must be satisfied when setting the start line (ss17 to 10) and end line (se17 to 10) of the 1 st screen driving position register (r14) and the start line (ss27 to 20) and end line (se27 to 20) of the 2 nd screen driving position register (r15) for the hd66770. note that incorrect display may occur if the restrictions are not satisfied. table 46: restrictions on the 1 st /2 nd screen driving position register settings 1 st screen driving (spt = 0) register setting display operation (se17 to 10) ? (ss17 to 10) = nl full screen display normally displays (se17 to 10) to (ss17 to 10) (se17 to 10) ? (ss17 to 10) < nl partial display normally displays (se17 to 10) to (ss17 to 10) in all other display area refers to the output level based on the pt setting. (non-display) (se17 to 1) ? (ss17 to 10) > nl setting disabled note 1: ss17 to 10 <= se17 to 10 <= afh note 2: setting se27 to 20 and ss27 to 20 are invalid. 2 nd screen driving (spt = 1) register setting display operation ((se17 to 10) ? (ss17 to 10)) + ((se27 to 20) ? (ss27-20)) = nl full screen display normally displays (se17 to 10) to (se17 to 10) ((se17 to 10) ? (ss17 to 10)) + ((se27 to 20) ? (ss27 to 20)) < nl partial display normally displays (se27 to 20) to (ss17 to 10) in all other display area refers to the output level based on the pt setting. (non-display) ((se17 to 10) ? (ss17 to 10)) + ((se27 to 20) ? (ss27 to 20)) > nl setting disabled table 47 note 1: ss17 to 10 <= se17 to 10 < ss27 to 20 <= se27 to 20 <= afh note 2: (se27 to 20) ? (ss17 to 10) <= nl
hd66770 rev.1.1 / april 2002 89 the driver output can not be set for non-display area during the partial display. determine based on characteristic of the display panels. source output in non-display area pt1 pt0 positive polarity negative polarity gate output in non- display area 0 0 v63 v0 normal operation 0 1 v63 v0 vgoff 1 0 gnd gnd vgoff 1 1 hi-z hi-z vgoff table 48 refer to the following flow to set up the partial display. full screen display pt1 ? 0 = 00 set ss/se bits wait (more than 2 frames) pt1 ? 0 = 01 or pt1 ? 0 = 10 or pt1 ? 0 = 11 partial display on set ss/se bits full screen display figure 78 screen division drive set up flow full screen drive set up flow set if necessary
hd66770 rev.1.1 / april 2002 90 absolute maximum ratings table 49 item symbol unit value notes* power supply voltage (1) vcc v -0.3 to + 4.6 1, 2 power supply voltage (2) ddvdh- gnd v -0.3 to + 4.6 1, 3 input voltage vt v -0.3 to vcc + 0.3 1 operating temperature topr c -40 to + 85 1, 4 storage temperature tstg c -55 to + 110 1, 5 notes: 1.if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limit is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. 2. vcc 3 gnd must be maintained 3.ddvdh 3 gnd must be maintained. 4.dc characteristics and ac characteristics of shipping chips and shipping wafer are guaranteed at 85 c. 5.this temperature specifications apply to the tcp package.
hd66770 rev.1.1 / april 2002 91 dc characteristics (v cc = 1. 8 to 3. 3 v, ta = ? 40 to +85c* 1 ) table 50 item symbol unit test condition min typ max notes input high voltage v ih v v c c = 1.8 to 3. 3 v 0.7 v cc ? v cc 2, 3 input low voltage v il v v cc = 1 . 8 to 3. 3 v ? 0.3 ? 0.15v cc 2, 3 output high voltage (1) (db0-15 pins) v oh1 v i oh = ? 0.1 ma 0.75v cc ? ? 2 output low voltage (1) (db0-15 pins) v ol1 v v cc = 1. 8 to 2.4 v, i ol = 0.1 ma ? ? 0.2 v cc 2 vcc = 2.4 to 3.3 v, i ol = 0.1 ma ? ? 0.15v cc 2 i/o leakage current i li a vin = 0 to v cc ? 1 ? 1 4 current consumption during normal operation (v cc ? gnd) i op a r - c oscillation v cc = 3.0 v , ta = 25c f osc = 177 khz ( 176 duty), ram data : 0000h ? 140 210 5, 6 current consumption during standby mode (v cc ? gnd) i st a v cc = 3 v, ta = 25c ? 0.1 5 lcd drive power supply current (ddvdh ? gnd) i lcd a v cc = 3.0 v, v lcd = 5.5 v vdh=5.0v cr oscillation; f osc = 177 khz ( 176 duty), ta = 25c, ram data : 0000h, rev =" 0 " , sap = "001", vrn4-0 = "0", vrp4-0 = "0", pkp52-00 = "0", prp12-00 = "0", vrn4-0 = vrp4-0 = "0", pkp52-00 = "0", prp12-00 = "0" ? 295 400 5,6 lcd drive voltage (ddvdh ? gnd) v lcd v 4.5 ? 5. 5 output voltage deviation vo m v ? 5 ? 7 dispersion of the average output voltage v m v ? ? 8
hd66770 rev.1.1 / april 2002 92 ac characteristics (v cc = 1 . 8 to 3. 3 v, ta = ? 40 to +85c* 1 ) clock characteristics (v cc = 1. 8 to 3.3 v) table 51 item symbol unit test condition min typ max notes external clock frequency fcp khz v cc = 1 . 8 to 3. 3 v 100 200 600 9 external clock duty ratio duty % v cc = 1 . 8 to 3. 3 v 45 50 55 9 external clock rise time trcp s v cc = 1 . 8 to 3. 3 v ? ? 0.2 9 external clock fall time tfcp s v cc = 1 . 8 to 3.3 v ? ? 0.2 9 r-c oscillation clock f osc khz rf = 24 0k w , v cc = 3 v 152 190 228 10 68-system bus interface timing characteristics normal write mode (hwm=0) (vcc = 1. 8 to 2.4 v) table 52 item symbol unit test condition min typ max enable cycle time write t cyce ns figure 1 600 ? ? read t cyce ns figure 1 800 ? ? enable high-level pulse width write pw eh ns figure 1 90 ? ? read pw eh ns figure 1 350 ? ? enable low-level pulse width write pw el ns figure 1 300 ? ? read pw el ns figure 1 400 ? ? enable rise/fall time t er , t ef ns figure 1 ? ? 25 set up time (rs, r/w to e, cs*) t ase ns figure 1 10 ? ? address hold time t ahe ns figure 1 5 ? ? write data set up time t dswe ns figure 1 60 ? ? write data hold time t he ns figure 1 15 ? ? read data delay time t ddre ns figure 1 ? ? 200 read data hold time t dhre ns figure 1 5 ? ?
hd66770 rev.1.1 / april 2002 93 high-speed write mode (hwm=1) (vcc = 1. 8 to 2. 4 v) table 53 item symbol unit test condition min typ max enable cycle time write t cyce ns figure 1 2 00 ? ? read t cyce ns figure 1 8 00 ? ? enable high-level pulse width write pw eh ns figure 1 9 0 ? ? read pw eh ns figure 1 3 50 ? ? enable low-level pulse width write pw el ns figure 1 9 0 ? ? read pw el ns figure 1 4 00 ? ? enable rise/fall time t er , t ef ns figure 1 ? ? 25 set up time (rs, r/w to e, cs*) t ase ns figure 1 10 ? ? address hold time t ahe ns figure 1 5 ? ? write data set up time t dswe ns figure 1 60 ? ? write data hold time t he ns figure 1 15 ? ? read data delay time t ddre ns figure 1 ? ? 200 read data hold time t dhre ns figure 1 5 ? ? normal write mode (hwm=0) (vcc = 2. 4 to 3 . 3 v) table 54 item symbol unit test condition min typ max enable cycle time write t cyce ns figure 1 250 ? ? read t cyce ns figure 1 500 ? ? enable high-level pulse width write pw eh ns figure 1 40 ? ? read pw eh ns figure 1 2 50 ? ? enable low-level pulse width write pw el ns figure 1 70 ? ? read pw el ns figure 1 2 00 ? ? enable rise/fall time t er , t ef ns figure 1 ? ? 25 set up time (rs, r/w to e, cs*) t ase ns figure 1 10 ? ? address hold time t ahe ns figure 1 5 ? ? write data set up time t dswe ns figure 1 60 ? ? write data hold time t he ns figure 1 15 ? ? read data delay time t ddre ns figure 1 ? ? 200 read data hold time t dhre ns figure 1 5 ? ?
hd66770 rev.1.1 / april 2002 94 high-speed write mode (hwm=1) (vcc = 2. 4 v to 3.3 v) table 55 item symbol unit test condition min typ max enable cycle time write t cyce ns figure 1 1 00 ? ? read t cyce ns figure 1 5 00 ? ? enable high-level pulse width write pw eh ns figure 1 4 0 ? ? read pw eh ns figure 1 2 50 ? ? enable low-level pulse width write pw el ns figure 1 4 0 ? ? read pw el ns figure 1 2 00 ? ? enable rise/fall time t er , t ef ns figure 1 ? ? 25 set up time (rs, r/w to e, cs*) t ase ns figure 1 10 ? ? address hold time t ahe ns figure 1 5 ? ? write data set up time t dswe ns figure 1 60 ? ? write data hold time t he ns figure 1 15 ? ? read data delay time t ddre ns figure 1 ? ? 200 read data hold time t dhre ns figure 1 5 ? ?
hd66770 rev.1.1 / april 2002 95 8 0 -system bus interface timing characteristics normal write mode (hwm=0) (vcc = 1. 8 to 2.4 v) table 56 item symbol unit test condition min typ max bus cycle time write t cycw ns figure 2 6 00 ? ? read t cycr ns figure 2 800 ? ? write low -level pulse width pw lw ns figure 2 90 ? ? read low -level pulse width pw lr ns figure 2 350 ? ? write high-level pulse width pw hw ns figure 2 30 0 ? ? read high -level pulse width pw hr ns figure 2 400 ? ? write/read rise/fall time t wrr, wrf ns figure 2 ? ? 25 setup time (rs to cs* , wr*, rd* ) t as ns figure 2 10 ? ? address hold time t ah ns figure 2 5 ? ? write data set up time t dsw ns figure 2 60 ? ? write data hold time t h ns figure 2 15 ? ? read data delay time t ddr ns figure 2 ? ? 200 read data hold time t dhr ns figure 2 5 ? ? high-speed write mode (hwm=1) (vcc = 1. 8 to 2.4 v) table 57 item symbol unit test condition min typ max bus cycle time write t cycw ns figure 2 2 00 ? ? read t cycr ns figure 2 800 ? ? write low -level pulse width pw lw ns figure 2 90 ? ? read low -level pulse width pw l r ns figure 2 350 ? ? write high-level pulse width pw hw ns figure 2 9 0 ? ? read high -level pulse width pw hr ns figure 2 400 ? ? write/read rise/fall time t wrr, wrf ns figure 2 ? ? 25 set up time (rs to cs* , wr*, rd* ) t as ns figure 2 10 ? ? address hold time t ah ns figure 2 5 ? ? write data set up time t dsw ns figure 2 60 ? ? write data hold time t h ns figure 2 15 ? ? read data delay time t ddr ns figure 2 ? ? 200 read data hold time t dhr ns figure 2 5 ? ?
hd66770 rev.1.1 / april 2002 96 normal write mode (hwm=0) (vcc = 2.4 to 3.3 v) table 58 item symbol unit test condition min typ max bus cycle time write t cycw n s figure 2 25 0 ? ? read t cycr ns figure 2 5 00 ? ? write low -level pulse width pw lw ns figure 2 40 ? ? read low -level pulse width pw lr ns figure 2 2 50 ? ? write high-level pulse width pw hw ns figure 2 70 ? ? read high -level pulse width pw hr ns figure 2 2 00 ? ? write/read rise/fall time t wrr, wrf ns figure 2 ? ? 25 set up time (rs to cs* , wr*, rd* ) t as ns figure 2 10 ? ? address hold time t ah ns figure 2 5 ? ? write data setup time t dsw ns figure 2 60 ? ? write data hold time t h ns figure 2 15 ? ? read data delay time t ddr ns figure 2 ? ? 200 read data hold time t dhr ns figure 2 5 ? ? high-speed write mode (hwm=1) (vcc = 2. 4 to 3.3 v) table 59 item symbol unit test condition min typ max bus cycle time write t cyc w ns figure 2 1 00 ? ? read t cycr ns figure 2 5 00 ? ? write low -level pulse width pw lw ns figure 2 40 ? ? read low -level pulse width pw lr ns figure 2 2 50 ? ? write high -level pulse width pw hw ns figure 2 4 0 ? ? read high -level pulse width pw hr ns figure 2 2 00 ? ? write/read rise/fall time t w rr , w rf ns figure 2 ? ? 25 set up time (rs to cs* , wr*, rd* ) t as ns figure 2 10 ? ? address hold time t ah ns figure 2 5 ? ? write data set up time t dsw ns figure 2 60 ? ? write data hold time t h ns figure 2 15 ? ? read data delay time t ddr ns figure 2 ? ? 200 read data hold time t dhr ns figure 2 5 ? ?
hd66770 rev.1.1 / april 2002 97 clock synchronized serial interface timing characteristics (vcc = 1.8 to 2.4 v) table 60 item symbol unit test condition min typ max serial clock cycle time write (received) t s cyc us figure 3 0.1 ? 20 read (transmitted) t s cyc us figure 3 0.25 ? 20 serial clock high-level pulse width write (received) t s ch ns figure 3 40 ? ? read (transmitted) t s ch ns figure 3 120 ? ? serial clock low-level pulse width write (received) t s cl ns figure 3 40 ? ? read (transmitted) t s cl ns figure 3 120 ? ? serial clock rise/fall time t scr, scf ns figure 3 ? ? 20 chip select s et up time t cs u ns figure 3 2 0 ? ? chip select hold time t ch ns figure 3 60 ? ? serial input data set up time t s isu ns figure 3 3 0 ? ? serial input data hold time t s i h ns figure 3 30 ? ? serial input data delay time t sod ns figure 3 ? ? 200 serial input data hold time t so h ns figure 3 5 ? ?
hd66770 rev.1.1 / april 2002 98 (vcc = 2.4 to 3.3 v) table 61 item symbol unit test condition min typ max serial clock cycle time write (received) t s cyc us figure 3 0.1 ? 20 read (transmitted) t s cyc us figure 3 0.15 ? 20 serial clock high-level pulse width write (received) t s ch ns figure 3 40 ? ? read (transmitted) t s ch ns figure 3 70 ? ? serial clock low-level pulse width write (received) t s cl ns figure 3 40 ? ? read (transmitted) t s cl ns figure 3 70 ? ? serial clock rise/fall time t scr, scf ns figure 3 ? ? 20 chip select s et up time t cs u ns figure 3 2 0 ? ? chip select hold time t ch ns figure 3 60 ? ? serial input data set up time t sisu ns figure 3 3 0 ? ? serial input data hold time t s i h ns figure 3 30 ? ? serial output data delay time t sod ns figure 3 ? ? 130 serial output data hold time t so h ns figure 3 5 ? ? reset timing characteristics (v cc = 1. 8 to 3. 3 v) table 62 item symbol unit test condition min typ max reset low-level width t res ms figure 4 1 ? ? reset ris e time t r res us figure 4 ? ? 10
hd66770 rev.1.1 / april 2002 99 electrical characteristics notes 1. for bare die and wafer products, specified up to 85 c . 2. the following three circuits are i pin , i/o pin , o pin configurations . pins: reset*, cs*, e/wr */scl rw/rd rs , rw/rd, rs, osc1, im2-1, im0/id, test1 , test v cc pmos nmos gnd pins: osc1, cl1, flm, m , disptmg gcl, gda, gcs*, eq, dcclk vcc pmos nmos gnd pins: db15 -db2, db1 ?^ sd0 ?c db0/sdi figure 79 i/o pin configuration gnd pmos output data output enable (input circuit) vcc nmos (tri-state output circuit) vcc pmos nmos
hd66770 rev.1.1 / april 2002 100 3.the test pin must be grounded and the im2/1 and im0/ id pins must be grounded or c onnected to vcc. 4.this exclude the current flowing through output drive moss. 5.this exclude the current flowing through the input/output units. the input level must be fixed high or low because through current increases if the cmos input is left floating. even if the cs pin is low or high when an access with the interface pin is not performed, current consumption does not change. 6. the following show the relationship between the operation frequency (fosc) and c urrent consumption (icc) (figure). 7.output-voltage deviation is the difference of output voltage between the pins next to each other. the pins output same data, and output voltage deviation is only for reference. 8. dispersion of the average output voltage is the difference of the average of output voltage between chips next to each other. 9.applies to the external clock input (figure). figure 81 external clock supply iop (ua) r-c, oscillation frequencies: fosc (khz) 400 200 0 vcc = 3v 100 300 200 400 500 600 300 280 0 vdh (v) 4.0 4.5 5.0 vcc = 3v , ddvdh = 5.5v 320 600 t yp. 260 240 220 200 t yp. i lcd (ua) figure 80 relationship between the operation frequency and current consumption duty = th 100% th+ tl x oscillator osc1 open osc2 t rcp t fcp th 0.7vcc 0.5vcc 0.3vcc 2k w tl
hd66770 rev.1.1 / april 2002 101 10.applies to the internal oscillator operations using external oscillation resistor rf ( figure and table). o s c 1 o s c 2 r f s i n c e t h e o s c i l l a t i o n f r e q u e n c y v a r i e s d e p e n d i n g o n t h e o s c 1 a n d o s c 2 p i n c a p a c i t a n c e , t h e w i r i n g l e n g t h t o t h e s e p i n s s h o u l d b e m i n i m i z e d . figure 82 internal oscillation (referential data) table 63 r-c oscillation frequency: fosc (khz) oscillation resistance ( k w ) vcc = 1. 8 v vcc = 2 v vcc = 2 . 4 v vcc = 3v vcc = 3. 3 v 110k w 299 333 372 401 411 150k w 234 258 284 305 311 180k w 202 222 243 258 263 200 k w 186 203 222 235 240 240 k w 160 173 188 198 202 270 k w 145 157 169 177 181 3 0 0 k w 132 143 153 161 163 3 9 0 k w 106 113 121 126 128 43 0 k w 97 104 110 115 116 ac characteristics test load circuits data bus: db15 to db0 test point 50pf figure 83 load circuit
hd66770 rev.1.1 / april 2002 102 timing characteristics 68-system bus operation figure 84 68-system bus timing notes: 1) pweh is specified in the overlapped period when cs* is low and e is high. 2) parallel data transfer is enabled on the db15-8 pins when the 8-bit bus interface is used. fix the db7-0 pins to vcc or gnd. rs r/w cs* e db0 to db15 db0 to db15 vih vil tase tahe pweh t ef t er t dswe t he wrire data t cyce tddre tdhre voh1 vol1 voh1 vol1 read data vih vil vil vil vih vih vil vih vil vih vil pwel vil vil note 1) note 2) note2)
hd66770 rev.1.1 / april 2002 103 80-system bus operation figure 85 80-system bus timing notes: 1) pwlw and pwlr is specified in the overlapped period when cs* is low and wr* or rd* is low. 2) parallel data transfer is enabled on the db15-8 pins when the 8-bit bus interface is used. fix the db7-0 pins to vcc or gnd. cs* twrf twrr tdsw tdhr voh1 vil vih vil rs wr * rd* vih vil vih vil tas tah vil vih pwlw, pwlr pwhw, pwhr tcycw, tcycr vih vih vil vih vil db0 to db15 db0 to db15 wrire data read data voh1 vol1 vol1 tddr note : 2 note : 2 th
hd66770 rev.1.1 / april 2002 104 clock synchronized serial interface operation r e s e t * tsch tsisu tscr vih vil vih vil vih vil tch vih vil vih vil tscl tsih vil tscyc input data vih start: s end: p sdo voh1 vol1 voh1 vol1 output data output data tsoh tscf vih cs* scl sdi vil vil input data tcsu tsod figure 86 clock synchronized serial interface timing figure 87 reset timing trre vil vil vil reset operation t res
hd66770 rev.1.1 / april 2002 105 maintenance history report p = page, l = line, - = blank rev date page maintenance history 6,9 chip thickness ( from 400 um to 550 um ) 19,35 ,37 vrh4 bit deleted and pon bit added 23 the explanation of rev bit changed 32 miswriting in the relation between gram data and grayscale level 47 miswriting in b02 62 miswriting in the formula for v60 67,71 setting flow changed ( put ? wait 2h period or longer ? before on) 69-70 the connection example changed ( condenser between vcom-vgoff deleted ) ( from v61p, v61n to v63p, v63n ) 81-92 ac characteristic added 0.6 2001.5.27 other miswriting 43 the example of the operation of high-speed consecutive writing to ram ( 8-bit bus interface ) added 0.7 2001.6.11 62,64 miswriting in voltage formula for v8 and v55 67 waiting time for color transition (from 200ms to 400ms ) 82,83 specification added ( current consumption, lcd drive power supply, deviation of output voltage, dispersion average of output voltage, rc oscillation clock) 84,86 specification changed ( 68 system bus interface/enable low- level pulse width pwel/ from 100ns to 70ns ) (80 system bus interface/ write high-level pulse width pwhw/ from 100ns to 70ns ) 89 graph for note 6 added 1.0 2001.6.22 90 table for note 10 added eq (from ? output the timing for equalizing low: normal display high: equalizing ? to ? indicate setting of the vcom output to its high-impedance state during transitions of vcom when vcom is being ac-cycled. low: vcomh or vcoml is being output on the vcom pin. high: vcom pin is in high- impedance state ? disptmg (from ? non-display ? to ? output voff signal ? ) 5 gcs (from ? transfer ? to ? transfer data ? ) bt2-0 (add the sentence below. ? lower amplification of the step-up circuit consumes less current. ? ) 21 slp (from ? only the following instructions can be executed during the sleep mode. ? to ? only serial transfer to a gate driver / power-supply ic and the following instructions can be executed during the sleep mode) ? vc2-0 (from ? vreg1 ? to ? vreg1out ? ) 22 vrl3-0 (from ? from 2 to 8.5 times ? to ? from ? 2 to ? 8.5 times ? ) 23 vdv4-0 (from ? when vcom is driven in a/c amplitude. ? to ? sets amplification factors for vcom and vgoff while vcom ac drive is being performed. ? ) 1.0-1 2001.10.2 26 table14 ( from ? vgh ? to ? vgon ? )
hd66770 rev.1.1 / april 2002 106 te (from ? driver/ic chip of the power driver ? to ? driver/power supply ic ? ) 27 * (from ? gate driver son after ? to ? gate driver / power supply ic soon after ? ) table18 (from ? the gate driver instruction ? to ? power supply ic (hd667p00) instructions ? ) 28 from ? ic chip of the power supply ? to ? power supply ic (hd667p00) ? 31 note (from ? common driver ? to ? gate driver ? ) ss17-0 (from ? common driver ? to ? gate driver ? ) se17-0 (from ? black display driving ? to ? bib-selection driving ? ) 32 se27-0 (from ? 4fh ? to ? afh ? ) 40 3. (from ? b-pattern lc ac drive control ? to ? lcd driving ac control) ? 51 restriction on window address-range settings (from ? 3fh ? to ? 83h ? ) restriction on address settings during the window address (from ? hsa5 ? to ? hsa7 ? ) 63 from ? subtle adjustment ? to ? micro adjustment ? title for y axis of figure 60,61,and 62 ( from vertical writing to horizontal writing ) 66 add the number 1 and 2 to ? gradient adjusting register ? and ? amplitude adjusting register ? . 67 add the number 3 to ? micro-adjusting register ? . 68 add the sub-title ? block configuration ? for the title ? ladder registor/8 to 1 selector ? 75 corrected the waiting time ( from 400ms to 40ms) 76 corrected the title. ( from ? system structure example ? to ? example of system configuration ? ) 77 corrected note 4 (from ? following connection capacity if gd667p00 is not stated. ? to ? condensers connected to following terminals of hd667p00 are omitted. ? ) 78 corrected note 1 ( from hd667p0 to hd667p00 ) 1.0-1 2001.10.2 79 add the sentence at the end of the sentence. (follow the below serial transfer flow about each setting and then transfer must be executed.)
hd66770 rev.1.1 / april 2002 107 p = page, l = line, - = blank rev date page maintenance history delete unnecessary note from figure 72 ( 200khz) 81 correct note (from ? the rf resistance must be located near the osc1/osc2 pin on the chip. ? to ? the rf resistance must be located near the osc1/osc2 pin on the master side. ? ) 82 correct note (from ? specify the number of ac drive raster- rows and the necessity of eor so that dc bias is not generated the liquid crystal. ? to ? in an n-raster-row driving eor should be ? 1 ? so that dc bias voltage is not applied .) ? 83 correct the sentence ( l5, ? field interlace,,, ? to ? 3-field interlace,,, ? ) correct the title ( from ? timing of changing polarity ? to ? ac driving timing ? ) 84 add a sentence (in l5 ? the amount of blanking periods becomes 16h in a frame. ? ) 1.0-1 2001.10.2 86 correct a sentence (in l7-8 ? ,,,the 1 st and 2 nd screens must correspond to the lcd-driving duty set value. ? to ? ,,,the 1 st and 2 nd screens must be the number of lcd drive raster-rows or less. ? ) 7 change product model name. ? from hd66770 to hd667a70 ? 10 change product model name. ? from hd66770 to hd667b70 ? 33 add note 3 add grayscale reference-value adjusting resistor. (r3f) 37 add an explanation sentence for vdr1-0. 39 add grayscale reference-value adjusting resistor. (r3fh) 64-68 add grayscale reference-value adjusting resistor. 69,71 change a formula (r) for adding grayscale reference-value adjusting resistor. 77,78 change example chart of connection. (figure 69, and 70) 79 add new page, ? specification of capacitor ? . 1.1 2002.4.5 80 change a flow of ? display off ? (add ? eq=1 ? )

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